MU Electronics and Telecom Engineering (Semester 3)
Digital Electronics
December 2011
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) Perform the following operations :
(i) 101.11 × 100.11
(ii) (4C)H × (5A)H
(iii) Convert (77)s into Decimal number system
(iv) Find (10-33)10 using 2's complement number system
(v) Convert (1001100001110110)2 into Hexa-decimal number system.
10 M
1 (b) Draw state diagram of sequence detector to detect a non-overlapping sequence 01100. write its state table. Find the equivalent state if they are present
10 M

2 (a) Design lockout free Mod 12 up synchronous counter using JKMS flip flops.
10 M
2 (b) Do the following conversion of flip flops :
(i) JKMS to SR (ii) D to T
10 M

3 (a) Draw standard TTL 2 input NAND gate circuit, discuss its operation and draw its transfer characteristics
10 M
3 (b) For the following function implement the SOP and POS circuit
F(A,B,C,D)=?m (2,3,5,7,12) + ?d(6,13,14,15)
10 M

4 (a) For the following function find reduced Boolean equation using Quine McClusky method;
F(A,B,C,D)= ?m(1,3,4,6,9,11,12,14)+?d(2,5,8,15)
10 M
4 (b) Draw logic diagram of 4:1 multiplexer and explain its operation
10 M

5 (a) Design full adder using decode with active low outputs.
10 M
5 (b) Explain following characteristics of logic families;
(i) Propagation delay (ii) Noise margin (iii) Current parameters (iv) Figure of merit (v) Fan out
10 M

6 (a) Design a ROM which will convert BCD numbers into 2421 code.
10 M
6 (b) Use 5 Input, 3 Product, 4 Output PAL to realize followinng 3 functions.
10 M

Write short notes on any four of the following :
7 (a) CMOS logic family
5 M
7 (b) FPGA
5 M
7 (c) PLA
5 M
7 (d) Weighted and non-weighted codes
5 M
7 (e) Multiplexer tree
5 M

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