STUPIDSID
Extc
1(a)
Compare Combinational circuits with Sequential circuits.
5 M
1(b)
Compare Synchronous with Asynchronous counter.
5 M
1(c)
Compare TTL with CMOS logic families.
5 M
1(d)
Compare PLA with PAL.
5 M
2(a)
Write the VHDL code for 2-bit up-down counter with positive edge triggered clock.
10 M
2(b)
State and prove the De Morgan's theorem.
5 M
2(c)
Draw the block diagram of internal architecture of XC4000 family FPGA.
5 M
3(a)
Design synchronous counter using T-type flip flops for getting the following sequence: 0 → 2 → 4 → 6 → 0. Take care of lockout condition.
10 M
3(b)
Convert T-type flip flop into D-type flip flop.
5 M
3(c)
Write (AB)16 into its BCD code and Octal code.
5 M
4(a)
Implement the following Boolean equation using single 4:1 MUX and few logic gates:
F(P,Q,R,S) = ∏ M(0, 2, 5, 6, 7, 9, 12, 15).
F(P,Q,R,S) = ∏ M(0, 2, 5, 6, 7, 9, 12, 15).
10 M
4(b)
Compare FPGAs with CPLDs.
5 M
4(c)
Implement Y = A + B C using only NOR gates.
5 M
5(a)
Draw a neat circuit of BCD adder using IC7483 and explain.
10 M
5(b)
Using Quine McClusk, method, minimize the following:
F(P, Q, R, S) = ∑m(0, 1, 3, 7, 8, 9, 15) + d(2, 10, 11).
F(P, Q, R, S) = ∑m(0, 1, 3, 7, 8, 9, 15) + d(2, 10, 11).
10 M
6(a)
Design a Mealy type sequence detector circuit to detect a sequence 1101 using t-type flip flops.
10 M
6(b)
What is shift register? Explain any one type of shift register. Give its application.
10 M
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