STUPIDSID
1 (a)
Compare combinational circuit with sequential circuit
5 M
1 (b)
Compare TTL with CMOS logic families
5 M
1 (c)
Compare SRAM with DRAM
5 M
1 (d)
Compare FPGAs with CPLDs
5 M
2 (a)
State and prove De Morgan's theorem
10 M
2 (b)
Using Quine McClusky method, minimize the following :
F(A,B,C,D,E)= Σm(0,1,3,7,8,9,11,15,22,24,27)+d(6,16)
F(A,B,C,D,E)= Σm(0,1,3,7,8,9,11,15,22,24,27)+d(6,16)
10 M
3 (a)
Implement the following Boolean equations single 8:1 MUX and few logic gates:
F(A,B,C,D,E)=Σm(0,1,3,4,8,9,15)
F(A,B,C,D,E)=Σm(0,1,3,4,8,9,15)
10 M
3 (b)
Write (32)10 into its BCD code, and Ex3 code.
5 M
3 (c)
Implement Y=A+BC using only NOR gate
5 M
4 (a)
Draw a neat circuit of BCD adder using IC 7483 and explain
10 M
4 (b)
It is desired to develop the circuit for controlling a lamp on a staircase between 1st and 2nd floor of a building. Each floor is having only one switch. If a lamp is made 'ON' using switch of 1st floor, one should be able to switch it 'OFF' using a switch of 2nd floor and vice versa. design the circuit for the same. write the VHDL code for the same.
10 M
5 (a)
What is shift refister? Explain any one type of shift register. Give its application.
10 M
5 (b)
Convert D type flip flop into T type flip flop
5 M
5 (c)
Compare PAL with PLA
5 M
6 (a)
Design a synchronous counter using D type flip flop for getting the following sequence : 0-2-4-6-0. take care of lockout condition.
10 M
6 (b)
Explain any one application of Johnson counter
5 M
6 (c)
Draw the block diagram of internal architecture of XC9500 family CPLD and explain in brief.
5 M
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