STUPIDSID
Explain the following
1 (a)
For ECL and CMOS logic families define-
(i) noise margin (ii) fan-in (iii) fan-out
(i) noise margin (ii) fan-in (iii) fan-out
5 M
1 (b)
Compare Asynchronous and synchronous counter
5 M
1 (c)
Explain static RAM
5 M
1 (d)
Explain Master-Slave J.K Flip-Flop
5 M
2 (a)
Perform following operation using 2's compliment method-
(i) (28)10-(42)10 (ii) (52)10-(-18)10
(i) (28)10-(42)10 (ii) (52)10-(-18)10
5 M
2 (b)
Prove the following using Boolean algebra
\[\bar{A}BC+A\bar{B}C+ABC+AB\bar{C}=AB+BC+CA\]
\[\bar{A}BC+A\bar{B}C+ABC+AB\bar{C}=AB+BC+CA\]
5 M
2 (c)
Design 2 bit comparator
10 M
3 (a)
Minimum the following using Quine Mc Clusky method
F(A,B,C,D)=Σm(3,4,9,13,14,15) + Σd(5,6)
F(A,B,C,D)=Σm(3,4,9,13,14,15) + Σd(5,6)
10 M
3 (b)
Design synchronous counter using J.K flip-flop for the given sequence- 0-2-3-5-7-0
10 M
4 (a)
Design following Boolean equation using 4:1 mux
F(A,B,C,D)=Σ m(2,4,5,7,9,11,12)
F(A,B,C,D)=Σ m(2,4,5,7,9,11,12)
5 M
4 (b)
Compare EPROM and FLASH memories
5 M
4 (c)
Explain bidirectional 4 bit universal shift register
10 M
5 (a)
Explain 3:8 decoder
5 M
5 (b)
Explain Mealey machine and Moore machine
5 M
5 (c)
Write VHDL code for 3 bit binary down counter
10 M
6 (a)
Explain Architecture and features of FPGA
10 M
6 (b)
Implement X-OR gate using NAND
5 M
6 (c)
Convert (11810) in to (i) BCD (ii) Hexadecimal (iii) Octal
5 M
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