STUPIDSID
Solve any four question from Q.1(a, b, c,d, e)
1(a)
Compare NMOS & CMOS technology in VLSI design.
5 M
1(b)
Implement the following function using Dynamic CMOS logic \[ Y=\overline{A(B+C)}\]
5 M
1(c)
Compare Ripple carry adder with CLA.
5 M
1(d)
Explain working principle of flash memory.
5 M
1(e)
Explain importance of low power design.
5 M
2(a)
Compare the full scalling & constant voltage scalling models of MOSFET Demonstrate the effect of scalling on the area, delay, power consumption and current density of the device.
10 M
2(b)
Expalin transfer characteristic of NMOS inverter showing different regions, what is the effect of variation in W/L ratio?
10 M
3(a)
Draw 1T DRAM cell and explain it's write read hold & refresh operation.
10 M
3(b)
Explain scheme for multiplication on 101*010.
10 M
4(a)
Explain various techniques of clock generation & clock distribution .
10 M
4(b)
Consider a CMOS inverter circuit with following parameters
VDD=3.3v.
V To.n = 0.6v.
V To.p = 0.7v
Kn = 200μ A/v2
Kp= 80 μ A/v2
Calculate noise Margins of the circuit Consider KR = 2.5 & V To.n ≠V ro.p
VDD=3.3v.
V To.n = 0.6v.
V To.p = 0.7v
Kn = 200μ A/v2
Kp= 80 μ A/v2
Calculate noise Margins of the circuit Consider KR = 2.5 & V To.n ≠V ro.p
10 M
5(a)
Draw JK Flip Flop using CMOS and explain the working.
10 M
5(b)
Draw CLA ( carry look head adder) carry chain using dynamic CMOS logic.
10 M
Write short note any three question from Q.6(a,b,c,d)
6(a)
Latch up in CMOS
7 M
6(b)
Sense Amplifier
7 M
6(c)
Interconnect scaling.
7 M
6(d)
4*4 Barel shifter.
7 M
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