STUPIDSID
1(a)
Consider a MOS structure with p-type semiconductor substrate doped to Na=1016/cm3,a
SIO2insulator with thickness of 500oand an oxide charge density of 1011/cm2,and a
polysilicon gate. Calculate the flat band voltage. Assume that ∅GC=-1.1V
SIO2insulator with thickness of 500oand an oxide charge density of 1011/cm2,and a
polysilicon gate. Calculate the flat band voltage. Assume that ∅GC=-1.1V
5 M
1(b)
What is Subthreshold conduction? What are the factors controlling the subthreshold current in long channel and short channel MOSFET?
5 M
1(c)
What is velocity Saturation? How does it effects the I-V characteristics of a Short channel MOSFET?
5 M
1(d)
Depletion mode n-channel device are not complementary to enhancement mode n-channel transistor and cannot match up with a p-channel enhancement mode transistor as load in an inverter circuit. Explain
5 M
1(e)
The boundaries of the valid input signal regions that define the Noise Margins In an inverter (VIH & V1L) are defined as the voltage points where the magnitude of the inverter voltage gain is equal to unity. Explain why?
5 M
2(a)
Explain the complete fabrication process steps for a CMOS inverter using n-well process with the help of cross sectional diagrams for all important masking steps
10 M
2(b)
Consider a silicon-gate PMOS transistor with the following parameters:
Substrate doping ND=1016/cm3,Gate doping ND=1020/cm3,QOX=4x1010qC/cm2,
tOX=0.10 μm
(i) Determine the threshold voltage VT0 under zero bias at room temperature. Note that ε=3.97εoand εsi=11.7ε.
(ii) Determine the type (p-type or n-type) and amount of the channel Implant (NI/cm2) required to change the threshold voltage from VT0 to - 1 V and + 3 V.
Substrate doping ND=1016/cm3,Gate doping ND=1020/cm3,QOX=4x1010qC/cm2,
tOX=0.10 μm
(i) Determine the threshold voltage VT0 under zero bias at room temperature. Note that ε=3.97εoand εsi=11.7ε.
(ii) Determine the type (p-type or n-type) and amount of the channel Implant (NI/cm2) required to change the threshold voltage from VT0 to - 1 V and + 3 V.
10 M
3(a)
In the inverter circuit what is meant by Zp.u and Zp.d ? Derive relation between zp.u and zp.d if an NMOS inverter is to be driver from another NMOS inverter.
10 M
3(b)
An enhancement mode n-channel MOSFET has the following parameters. Threshold voltage VT = 0.8 v. channel length modulation coefficient λ=0.05/V, μnCOX=20μA/V2.
Find the drain current for the following cases.
(i) Vg=5V, VD=4V, VS=2V.
(ii) Vg=2.8V, VD=5V, VS=1V.
Find the drain current for the following cases.
(i) Vg=5V, VD=4V, VS=2V.
(ii) Vg=2.8V, VD=5V, VS=1V.
10 M
4(a)
A reference inverter has (W/L)n =1/1 and (W/L)p=3/1. Draw the schematic and the stick diagram of a two input NAND gate and calculate the (W/L) ratios of transistors based on reference inverter design.
10 M
4(b)
Draw the mask layout of the circult designed in question 4(a) in n-substrate and p-well.
10 M
5(a)
Compare constant field scaling with constant voltage scaling and state advantages and limitations in both the methods. Show analytically how delay time, power density and current density are affected in terms of scaling factors In both the type of scaling methods.
10 M
5(b)
Implement the following Boolean function in CMOS logic.
\[ Y=\bar{\left(D+E+A\right).(D+C)} \]Draw the optimized stick diagram of the logic gate using Euler path.
\[ Y=\bar{\left(D+E+A\right).(D+C)} \]Draw the optimized stick diagram of the logic gate using Euler path.
10 M
6(a)
Draw the p-well CMOS inverter and explain the latch up effect in it. Why latch up must be prevented and what are the remedies to avoid the latch up problem in the circuit?
10 M
6(b)
Implement a 2:1 multiplexer circuit using CMOS transmission gates. Write a Verilog module for the circuit at switch level of abstraction. Write a test bench to check the functionality of the circuit.
10 M
Write short notes on any three
7(a)
Ion implantation.
7 M
7(b)
MOS capacitance.
7 M
7(c)
Design rules and their necessity.
7 M
7(d)
Short channel effects.
7 M
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