STUPIDSID
Solve any five from the following:
1 (a)
Explain Level 1 and Level 2 MOSFET model used in circuit simulator.
5 M
1 (b)
In 2 input CMOS NAND gate all PMOS transistor have \(\left ( \dfrac {W}{L} \right )=20 \) and all NMOS transistor have \( \left ( \dfrac {W}{L} \right )_n =10 \). Draw its equivalent CMOS inverter and find size of PMOS and NMOS transistor in the equivalent inverter circuit.
5 M
1 (c)
What are advantages & disadvantages of dynamic logic circuit.
5 M
1 (d)
Why sense amplifier is used in memory circuit. Explain its working.
5 M
1 (e)
How low power circuit is designed through voltage scaling.
5 M
1 (f)
Explain hot carrier in short channel MOSFET.
5 M
2 (a)
Compare resistive load inverter, saturated load inverter and CMOS inverter on the basis of Noise margins, power dissipation, area and delay.
10 M
2 (b)
Draw 2 input CMOS NOR gate and using equivalent inverter approach and derive expression for Vm' VIH' VOL and VOH.
10 M
3 (a)
Design clocked D-FF and implement using standard CMOS logic style.
10 M
3 (b)
Draw layout of six transistor CMOS SRAM using lambda rule.
10 M
4 (a)
Explain 4-bit x 4-bit array multiplier with the help of necessary hardware for the generation and addition of partial product.
10 M
4 (b)
Why ESD protection is required for CMOS chips. Explain various techniques of ESD protection.
10 M
5 (a)
Implement y=A (D+E)+BC using
i) Static CMOS style
ii) Pseudo NMOS logic style
iii) Dynamic logic style
Transmission Gate logic
i) Static CMOS style
ii) Pseudo NMOS logic style
iii) Dynamic logic style
Transmission Gate logic
10 M
5 (b)
What are different types of MOSFET scaling? Explain advantages and disadvantages of each using appropriate equations.
10 M
Write short notes on any four:
6 (a) (i)
3T-DRAM cell
5 M
6 (a) (ii)
Clock distribution in VLSI system
5 M
6 (a) (iii)
Barrel shifter.
5 M
6 (a) (iv)
C2MOS logic style
5 M
6 (a) (v)
1-bit shift register.
5 M
More question papers from VLSI Design