STUPIDSID
Solve any five:
1 (a)
Draw layout of 2 input CMOS NOR gate using lambda (λ) rules.
4 M
1 (b)
Implement Master Slave D Flip Flop using C2MOS logic style.
4 M
1 (c)
Explain various sources of power dissipation in CMOS Inverter.
4 M
1 (d)
Implement NOR based 2:4 decoder.
4 M
1 (e)
State various short channel effects and explain one of them.
4 M
1 (f)
Draw static CMOS NAND and NOR gates. Size all transistors in NAND and NOR gate to provide worst case equal rise and fall delay for both gates. Assume mobility of electron is two times higher than that of holes. Magnitude of threshold voltage for all transistor is same.
4 M
2 (a)
Draw six transistor CMOS SRAM cell. Describe various constraints that should be imposed on the devices for guranteeing safe read and write operation. Derive the equation that would help to size the transistors and also based on derived equations, discuss qualitatively relative sizing of transistors in the cell.
10 M
2 (b)
Implement \(Y=\overline{AB+ C(D+E)} \) using
i) Static CMOS logic
ii) Dynamic logic with pull up network
iii) Dynamic logic with pull down network.
iv) Pseudo NMOS logic.
i) Static CMOS logic
ii) Dynamic logic with pull up network
iii) Dynamic logic with pull down network.
iv) Pseudo NMOS logic.
10 M
3 (a)
With the help of neat cross sections and appropriate masks, give the process flow of N-well CMOS technology.
10 M
3 (b)
For CMOS Inverter with following parameters. \[ \begin {align*} & V_{TO.n} = 0.6V & \mu_n C_{ox}= 60\mu A/V^2, \left ( \dfrac {W}{L} \right )_n = 8 \\& V_{TO.p}= -0.7 V & \mu_p C_{ox} = 20 \mu A/V^2, \left ( \dfrac {W}{L} \right )_p = 12 \end{align*} \] Calculate noise margins and the switching threshold of the inverter. The power supply voltage VDD=3.3V.
10 M
4 (a)
Design clocked CMOS JK latch to implement the truth table shown below.
| Clk | J | K | Qn+1 |
| 1 | 0 | 0 | Qn |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | Qn (toggle) |
10 M
4 (b)
Explain 4×4 bit array multiplier with the help of necessary hardware for the generation and addition of partial product.
10 M
5 (a)
In two input CMOS NAND gate, μnCox=20μA/V2, μnCox=10μA/V2, and all PMOS have \[ \left ( \dfrac {W}{L} \right )_n = 20, \ V_{TO.n} = 1 \ V \ and \ V_{TO.p}=-1 V. \] If one of the input is held permenantly at VDD and other is switched from zero volts to VDD with zero rise time for a duration gather than fall delay of NAND gate and then switched back to zero volts with zero fall time, then calculate tpHL and tpHL. Assume VDD=5V and total load capacitance which is independent of MOSFET sizes is equal to 2PF.
10 M
5 (b)
With the help of suitable diagrams explain how clock is generated and stabilized in VLSI chip.
5 M
5 (c)
Explain with help of neat diagrams importance of power distribution network in VLSI chip.
5 M
Write short notes on (any four):
6 (a)
Flash memory.
5 M
6 (b)
Carry look ahead adder.
5 M
6 (c)
ESD protection circuit.
5 M
6 (d)
Barrel Shifter.
5 M
6 (e)
Interconnect scaling.
5 M
More question papers from VLSI Design