STUPIDSID
Answer any one question from Q1 and Q2
1 (a)
Explore MOSFET as active resistor. Give the necessary expressions.
8 M
1 (b)
With the help of circuit diagram, explain cascode configuration in brief. What are its merits and applications.
8 M
2 (a)
Give the analysis of differential amplifier. Mention the expressions for CMRR and ICMR.
8 M
2 (b)
Explain with suitable schematic, current source/sink. What are the limitations on output voltage?
8 M
Answer any one question from Q3 and Q4
3 (a)
Draw and explain voltage transfer curve of CMOS inverter. What is need of symmetry?
8 M
3 (b)
What is body effect? What are its impact on performance of CMOS ckt?
8 M
4 (a)
Give the expressions for static, dynamic power dissipations and power delay product. What are the ways to minimize these?
8 M
4 (b)
Derive the relationships between widths of n and p devices in CMOS logic. Why is it necessary to maintain certain ratio? Explain with suitable example.
8 M
Answer any one question from Q5 and Q6
5 (a)
Write VHDL code for 4 bit shift register for serial in serial out operation. Write test bench.
9 M
5 (b)
Compare function and procedure with suitable VHDL examples in detail.
9 M
6 (a)
Draw FSM diagram and write VHDL code for 4 bit UP/DOWN counter.
9 M
6 (b)
Explain any three VHDL attributes with suitable examples.
9 M
Answer any one question from Q7 and Q8
7 (a)
Compare PLD architecture with custom ASIC, general purpose processor and microcontroller in detail. What are its merits compared to all these?
8 M
7 (b)
What are the limitations of current PLD architectures?
8 M
8
Draw the architecture of FPGA in detail. Explore LUTs, routing resources, memory blocks and clock management methods.
16 M
Answer any one question from Q9 and Q10
9 (a)
What are the types of fault? Explain stuck open, short and stuck at 0, 1 faults in detail. At what stage of design / manufacturing do these occur?
8 M
9 (b)
Explore the need of design for testability with appropriate examples.
8 M
10 (a)
With the help of suitable schematic, explain TAP controller in detail.
8 M
10 (b)
Explain built in self test with example of suitable schematic.
8 M
Answer any one question from Q11 and Q12
11 (a)
What is supply and ground bounce? Explain power distribution techniques in brief.
9 M
11 (b)
What are wire parasitics? How to take care of them while routing?
9 M
12 (a)
Explain signal integrity issues and EMI immune chip design.
9 M
12 (b)
What are the techniques of power optimization? Explain in brief.
9 M
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