STUPIDSID
Answer any one question from Q1 and Q2
1 (a)
Explain device parasitic and their limitation on the performance of CMOS circuit.
10 M
1 (b)
Write short note on source follower.
6 M
2
Explain with schematic various types of CMOS Differential Amplifier.
16 M
Answer any one question from Q3 and Q4
3
Draw Schematic and explain any three types of CMOS Inverter wrt Gain, Bandwidth and Rout.
16 M
4 (a)
What is Technology Scaling? Explain various design rule checks in terms of λ.
12 M
4 (b)
Write short note on Dynamic power dissipation of CMOS Inverter.
4 M
Answer any one question from Q5 and Q6
5 (a)
Write VHDL Code for 16:1 Mux using 4:1 Mux as a component in structural style.
12 M
5 (b)
Differentiate between Function and Procedure with VHDL Coding.
6 M
6 (a)
Draw State diagram and write VHDL code for Traffic Light Controller.
12 M
6 (b)
Define Resolution function with VHDL Code.
6 M
Answer any one question from Q7 and Q8
7 (a)
Explain any four important specification of FPGA. Also explain the Significance of CLB's in FPGA.
8 M
7 (b)
Explain Antifusable Generic FPGA Architecture.
8 M
8 (a)
Enlist all the types of memory used in PLD's.
8 M
8 (b)
With the help of diagram explain SRAM and antifuse FPGA. What factors are considered to make a choice between SRAM and Antifuse FPGA.
8 M
Answer any one question from Q9 and Q10
9 (a)
Explain the significance of 'select', 'Capture' and 'shift' state in TAP controller.
8 M
9 (b)
Explain:
i) Partial scan and full scan
ii) Stuck at '1' and '0' faults.
i) Partial scan and full scan
ii) Stuck at '1' and '0' faults.
8 M
10 (a)
What is the need for testability? Explain the different electrical faults.
8 M
10 (b)
Explain Built in self Test? Differentiate between Online BIST and Offline BIST.
8 M
Answer any one question from Q11 and Q12
11 (a)
How to achieve the EMI immune chip design? Explain the parasitic involved in routing matrix.
9 M
11 (b)
Explain the following:
i) Supply and ground bounce
ii) Clock skew
iii) Clock jitter.
i) Supply and ground bounce
ii) Clock skew
iii) Clock jitter.
9 M
12 (a)
What is signal integrity? Explain the important issues in SOC design.
9 M
12 (b)
Explain in brief clock distribution in detail.
9 M
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