SPPU Electronics and Telecom Engineering (Semester 7)
VLSI Design & Technology
December 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Solve any one question from Q1 and Q2
1 (a) Write VHDL code for 8 bit serial in serial out shift register by structural & behavioural modelling methods.
7 M
1 (b) What is need of FPGA? List typical specifications of FPGA.
7 M
1 (b) Explain I/O architecture in detail.
6 M

2 (a) What are flip flop timings? What is meta-stability? What are solutions?
7 M
2 (b) Explore the architecture of CPLD in detail.
7 M
2 (c) What are different wire parasitics? How do they play important role in Routing?
6 M

Solve any one question from Q3 and Q4
3 (a) Derive the expressions for power dissipations in CMOS. What are the techniques to minimize the dissipations?
9 M
3 (b) Design CMOS logic for Y = AB + CDEFG+H. Compute area on chip.
9 M

4 (a) What is power delay product? Derive the expression for it. What is its Significance?
9 M
4 (b) Explain linear delay model in detail.
9 M

Solve any one question from Q5 and Q6
5 (a) Compare push-pull, current source & active load inverters with respect to voltage gain, voltage range, output resistance & bandwidth in detail.
8 M
5 (b) Draw the schematic of CMOS differential amplifier and give the expressions for voltage gain, output resistance. CMRR & ICMR.
8 M

6 (a) Draw common drain amplifier. Compare with common source & common gate amplifiers with respect to gain, output resistance & bandwidth.
8 M
6 (b) Draw & explain CMOS operational amplifier. Give the expressions for voltage gain & output resistance.
8 M

Solve any one question from Q7 and Q8
7 (a) What is need of DFT? Explain with suitable example.
8 M
7 (b) Explain fault models in detail.
8 M

8 (a) With the interface ports involved, explain JTAG in detail.
8 M
8 (b) What is partial & full scan path?
8 M



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