SPPU Electronics and Telecom Engineering (Semester 7)
VLSI Design & Technology
December 2016
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


Solve any one question from Q.1(a,b) & Q.2(a,b)
1(a) Write a short note on openstank architecture.
4 M
Solve any one question from Q.1(a,b,c)& Q.2(a,b,c)
1(a) State the difference between
i) Signal and variable
ii) Functions and procedures
6 M
Solve any one question from Q.1(a,b,c) & Q.2(a,b,c)
1(a) State the difference between
i) Signal and variable
ii) Functions and procedures
6 M
1(b) Explain cloud deployment models in detail.
6 M
1(b) Draw and explain the following for FPGA
i) Logic cell
ii) CLB
iii) Programmable switch matrix
iv) I/O block
8 M
1(b) Draw and explain the following for FPGA
i) Logic cell
ii) CLB
iii) Programmable switch matrix
iv) I/O block
8 M
1(c) What is the need of clock distribution? Explain techniques of clock distribution.
6 M
1(c) What is the need of clock distribution? Explain techniques of clock distribution.
6 M

2(a) Write VHDL code and test bench for D FLIP FLOP using function for clock event.
8 M
2(a) Elaborate characteristics of cloud computing.
6 M
2(a) Write VHDL code and test bench for D FLIP FLOP using function for clock event.
8 M
2(b) Explain with diagram SRAM and anti-fuse programming techniques used in FPGA?
6 M
2(b) Explain cloud computing reference model.
4 M
2(b) Explain with diagram SRAM and anti-fuse programming techniques used in FPGA?
6 M
2(c) What is floor planning? Explain in detail.
6 M
2(c) What is floor planning? Explain in detail.
6 M

Solve any one question from Q.3(a,b) & Q.4(a,b)
3(a) Draw and explain CMOS trasfer characteristics in detail showing all regions in the characteristics.
8 M
Solve any one question from Q.3(a,b) & Q.4(a,b)
3(a) Explain characteristics of virtuailizied enviroments in detail.
4 M
Solve any one question from Q.3(a,b)& Q.4(a,b)
3(a) Draw and explain CMOS transfer characteristics in detail showing all regions in the characteristics.
8 M
3(b) Design CMOS logic for \(Y=\overline{AB+CD+E}. \)/ Calculate W/L ratio for NMOS and PMOS area needed on chip.
10 M
3(b) Explain in detail KVM architecture.
6 M
3(b) Design CMOS logic for Y = AB+CD+E.Calculate W/L ratio for NMOS and PMOS area needed on chip.
10 M

4(a) Explain transmission gate. States its advantages. Implement a circuit of 2:1 multipelxer using transmission gate. Comment on the number of transistor required using transmission gates and conventional method.
10 M
4(a) How does virtual provisioning simplifies cloud storage management?
6 M
4(a) Explain transmission gate. States its advantages. Implement a circuit of 2:1 multiplexer using transmission gate. Comment on the number of transistor required using transmission gates and coneventional method.
10 M
4(b) Explain the following. i) Velocity saturation
ii) Body effect
iii) Hot electron effect
iv) Channel length modulation
8 M
4(b) Write a short note on Dynama.
4 M
4(b) Explain the following.
i) Velocity sturation
ii) Body effect
iii) Hot electron effect
iv) Channel length modulation
8 M

Solve any one question from Q.5(a,b) & Q.6(a,b)
5(a) Explain common source amplifier with the help of circuit diagram. Draw AC equivalent circuit and expression for voltage gain, output resistance.
8 M
Solve any one question from Q.5(a,b) & Q.6(a,b)
5(a) Explain vritual mochine migration techniques in detail.
10 M
Solve any one question from Q.5(a,b)& Q.6(a,b)
5(a) Explain common source amplifier with the help of circuit diagram. Draw AC equivalent circuit and expression for voltage gain, output resistance.
8 M
5(b) Explain device parasitic and their limitation on the performance of CMOS circuits.
8 M
5(b) Elaborate process of SLA commitment.
6 M
5(b) explain device parastic and their limitation on the performance of CMOS circuits.
8 M

6(a) Draw and explain difference amplifier using MOS transistors.
8 M
6(a) How opennebula cloud models and manages VMS in virtualized infrastructure.
8 M
6(a) Draw and explain difference ampliifier using MOS transistors.
8 M
6(b) Draw and explain current sink and source circuits.
8 M
6(b) Explain scheduling techniques in cloud computing.
8 M
6(b) Draw and explain current sink and source circuits.
8 M

Solve any one question from Q.7(a,b) & Q.8
7(a) Explain the need of design for testability. Explain scan path testing.
8 M
Solve any one question from Q.7(a,b,c) & Q.8(a,b)
7(a) Explain the model for federated cloud computing.
6 M
Solve any one question from Q.7(a,b)& Q.8
7(a) Explain the need of design for testability. Explain scan path testing.
8 M
7(b) Expalin stuck-at-0 and stuck-at-1 faults with example.
8 M
7(b) Explain performance related issues for HPC in cloud computing.
6 M
7(b) Explain stuck-at-0 stuck-at-1 faults with example.
8 M
7(c) What do you mean by SLA? Elaborate various types of SLA.
6 M

8 Write short note on.
a) TAP controller with state diagram.
b) Built In Self Test(BIST)
16 M
8 Write short note on.
a) TAP controller with state diagram.
b) Built In Self Test (BIST)
18 M
8(a) Write a short note on.
i)SOAP versus REST.
ii) Work flow modeling.
9 M
8(b) Explain traditional approaches of SLA.
9 M

Solve any one question from Q.9(a,b) & Q.10(a,b)
9(a) Write a short note on following offering on saas segment to improve information security.
i) Email filtering
ii) Web content filtering
iii) Vulnerability management
iv) Identity management - as - a - service(Ioass)
12 M
9(b) What are data security risks? How will you mitigate these risks.
4 M

10(a) Explain in detail IAM architecture.
8 M
10(b) Explain information security concerns associated with data stored in cloud.
8 M



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