STUPIDSID
Answer any one question from Q1 and Q2
1 (a)
Draw the schematics of current source/sink. Explain in brief. What are limitations? How are these eliminated in cascode?
8 M
1 (b)
With the expressions for voltage gain & output resistance, explain common source, common drain & common gate amplifiers in brief. Mention application of each.
8 M
2 (a)
Explain CMOS op-amp with circuit diagram in detail. What is functionality of each stage?
8 M
2 (b)
Draw ac equivalent circuit of MOSFET for low and high frequency. How do parasitics play important role?
8 M
Answer any one question from Q3 and Q4
3 (a)
Derive the expressions for static dissipation, dynamic dissipation and power delay product.
8 M
3 (b)
With the help of voltage transfer curve, explain CMOS inverter in detail. What is significance of each region? What weak 0 & weak 1 ?
8 M
4 (a)
What is noise margin? Give expressions. How does it help designer?
8 M
4 (b)
Design CMOS combo logic for P = AB + CDE + FG. Compute area on chip.
8 M
Answer any one question from Q5 and Q6
5 (a)
Write VHDL code and test bench for 1001 mealy sequence detector.
9 M
5 (b)
What are synthesizable and non-synthesizable statements? Give VHDL code examples of each.
9 M
6 (a)
What is role of synchronizer in metastability problem? Explain any one synchronizer with timing diagram.
9 M
6 (b)
Write VHDL code for 1000 bit shift register.
9 M
Answer any one question from Q7 and Q8
7
Draw FPGA architecture in detail. Explain Logic cell, Routing resources, Flip-flops, I/O Blocks, JTAG, LUTs, Memory blocks, clock management etc. Give specifications of FPGA.
16 M
8 (a)
What is neet of PLD? Explain technologies involved in detail.
8 M
8 (b)
Compare CPLD & FPGA in detail. List typical specifications of CPLD.
8 M
Answer any one question from Q9 and Q10
9 (a)
What is BIST? Give suitable example of it.
8 M
9 (b)
What are types of fault? What are their sources? What is meant by fault coverage?
8 M
10 (a)
What is need of DFT? Explain block diagram of scan method. Give any case study example.
8 M
10 (b)
What is need of TAP? With the help of block diagram, explain TAP controller in brief.
8 M
Answer any one question from Q11 and Q12
11 (a)
What is supply and ground bounce? Explore power distribution techniques.
9 M
11 (b)
Draw & explain I/O architecture.
9 M
12 (a)
Explore signal integrity issues in chip design. How to tackle them.
9 M
12 (b)
What is need of power optimization? Explain in detail.
9 M
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