STUPIDSID
1 (a)
Mention the types of HDL descriptions. Explain how half adder can be modelled in VHDL and verilog in any one description method.
10 M
1 (b)
Discuss the shift operators used in VHDL and verilog with example.
4 M
1 (c)
Write switch level description of an inverter in verilog.
3 M
1 (d)
A=110, B=111, C=011000, D=111011, evaluate (A and not B) or (C nor 2 and D).
3 M
2 (a)
Write a data flow description in VHDL for two-bit magnitude comparator. Show simulation waveforms.
8 M
2 (b)
Write a verilog code to realize D-latch with active high enable in data flow modelling method. Show simulation waveforms.
6 M
2 (c)
Write HDL code for 2×2 combinational array multiplier (VHDL or verilog).
6 M
3 (a)
Write a VHDL code to realize JK flip flop with synchronous reset.
4 M
3 (b)
Write verilog description to realize.
i) 3-bit counter using case statement
ii) 4:1 multiplexer using if statement
i) 3-bit counter using case statement
ii) 4:1 multiplexer using if statement
6 M
3 (c)
Explain Booth algorithm with an example and write the flow chart of Booth multiplication algorithm. Write VHDL or verilog code 4×4 bit Booth algorithm.
10 M
4 (a)
Write the VHDL description of a 2:4 decoder using structural modelling method.
5 M
4 (b)
Write the excitation table of an SRAM memory cell and write its structural description in VHDL or verilog.
10 M
4 (c)
Write the structural description of a 4-bit asynchronous down counter using generate statement in verilog.
5 M
5 (a)
Write a VHDl/verilog code to convert unsigned binary to an integer using procedure/task.
6 M
5 (b)
Write a VHDL/verilog description to find the floating sum \[ y=\sum^{3}{i=0} (-1)^i (x)^i; 0
6 M
5 (c)
Write a VHDL code to write integers to a file
8 M
6 (a)
Discuss about mixed type description and its advantages. Illustrate with an example
6 M
6 (b)
Write short notes on VHDL package and discuss the syntax of declaration of a package
7 M
6 (c)
Write the VHDl/verilog description of 16×8 SRAM.
7 M
7 (a)
Explain how a VHDL entity can be invoked from a verilog module with full adder as an example
10 M
7 (b)
Write the mixed language description to invoke verilog module of JK flip-flop with clear from VHDL module
10 M
8 (a)
Discuss mapping of signal assignment statement and level with suitable examples.
5 M
8 (b)
Explain mapping of if-else statement with a suitable example
5 M
8 (c)
Show the synthesis information extracted from the listing shown below:
Package codes is
type op is (add, mul, divide, none);
end;
work codes;
entity ALUS2 is
port (a, b; in std_logic_vector (3 downto 0);
cin: in std_logic;
opc: in op;
z: out std_logic_vector (7 downto 0);
cout: out std_logic;
err: out Boolean);
end ALUS2;
Package codes is
type op is (add, mul, divide, none);
end;
work codes;
entity ALUS2 is
port (a, b; in std_logic_vector (3 downto 0);
cin: in std_logic;
opc: in op;
z: out std_logic_vector (7 downto 0);
cout: out std_logic;
err: out Boolean);
end ALUS2;
10 M
More question papers from Fundamentals of HDL