Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary


1 (a) Write switch level description in VHDL, for the inverter circuit with NMOS and PMOS. Explain the advantages of this type description over the other types.
8 M
1 (b) Write the result of all shift and rotate operations in VHDL after applying them to a 7-bit vector A=1001010 for one position.
6 M
1 (c) Explain verilog data types.
6 M

2 (a) Design 2×2 unsigned combinational array multiplier and write the VHDL. Code for the same.
8 M
2 (b) Draw the block diagram of a 3-bit carry look ahead adder and write data flow description for its Boolean functions in verilog.
8 M
2 (c) Explain signal declaration and assignment with examples.
4 M

3 (a) Write the behavioural description for half adder using verilog.
4 M
3 (b) Write the VHDL, description for SR flip flop using case statement and variable declaration.
6 M
3 (c) Explain Booth algorithm with flow chart. Write VHDL description to multiply two 4-bit numbers -5 and 7.
10 M

4 (a) Write gate level diagram and verilog structural description for D-latch.
8 M
4 (b) What is binding? Discuss binding between
i) Entity and architecture
ii) Library and component
8 M
4 (c) What are the advantages of HDL structural description?
4 M

5 (a) Write a VHDL function to find the greater of two signed numbers.
6 M
5 (b) Write HDL description to convert signed binary to the integer using task.
8 M
5 (c) What is the significance of procedure, task and function? Differentiate between them.
6 M

6 (a) Describe the development of HDL code for an arithmetic logic unit and write the verilog code for 16-bit ALU to perform 8 operations.
8 M
6 (b) Write the block diagram and function table of a 3SRAM. Using this write a verilog description for 16×8 SRAM.
8 M
6 (c) How to attach a package to the VHDL. Module? Explain with example.
4 M

7 (a) Write mixed language description of a JK flip flop with clear, invoking VHDL, entity from verilog module.
8 M
7 (b) Describe full adder using two half adder invoking verilog module from VHDL entity.
8 M
7 (c) Explain the necessity of mixed language description.
4 M

8 (a) What is synthesis? With a neat flow chart, explain the steps invoked in a synthesis process.
6 M
8 (b) Design gate level synthesis and write VHDL, description for the information given below:
td style="text-align: center;">

z=b

z=b+4

z=b/2

z=15

z=15

InputOutput
a b z

00

01

10

11

xx

0-7

0-7

0-7

xx

8-15

14 M



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