STUPIDSID
1(a)
Describe VHDL scalar data types with an example.
8 M
1(b)
Explain composite and access data types with an example for each.
8 M
1(c)
\( \text{Let}\ \vec{D}=(2y^2z-8xy)\hat{a}_x+(4xyz-4x^2)\hat{a}_y+(2xy^2-4z)\hat{a}_z.\) Determine the total charge within a volume of 10-14m3 located at P(1, -2, 3).
5 M
2(a)
Write a VHDL code in data flow description for a 2 bit magnitude comparator with help of truth table and simplified Boolean expression.
12 M
2(b)
Write a HDL codes for 2×2 bit combinational array multiplier (Both VHDL and verilog).
8 M
3(a)
Write behavioral description of a half-adder in VHDL and verilog with propagation delay of 10ns. Discuss features of their description in VHDL and verilog.
8 M
3(b)
Mention the names of sequential statements associated with behavioral description.
2 M
4(a)
Explain with suitable examples, how binding is achieved in VHDL between.
i) Entity and architecture
ii) Entity and component
iii) Library and module.
i) Entity and architecture
ii) Entity and component
iii) Library and module.
6 M
4(b)
Write a structural description using VHDL to implement a 2:1 multiplexer with active low enable.
10 M
4(c)
Explain the use of generate statement. Write down format for it both in VHDL and verilog.
4 M
5(a)
Explain the following syntax with examples: i) Procedure; ii) Task; iii) Function.
6 M
5(b)
Write verilog description to convert signed binary to the integer using task.
8 M
5(c)
Write a VHDL function to find the greater of two signed numbers.
6 M
6(a)
Describe procedure for invoking a VHDL entity from a verilog module and a verilog module from a VHDL module.
8 M
6(b)
Develop mixed-language description of a 9 bit adder.
8 M
6(c)
Write note on VHDL packages.
4 M
7(a)
What is the necessity of mixed type description?
4 M
7(b)
Describe the development of HDL code for an ALU and write VHDL/verilog code for ALU shown below. Assume the following operation: Addition, multiplication, division, no operation.
:!mage
:!mage
16 M
8(a)
What is synthesis? List the general steps involved in synthesis.
8 M
8(b)
Write VHDL code for signal assignment statement code in verilog using gate level diagram. Write structural code in verilog using gate level diagram.
12 M
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