STUPIDSID
1 (a)
Describe VHDL scalar data types with an example.
8 M
1 (b)
Explain shift and rotate operators in HDL with an example.
8 M
1 (c)
Write a note on simulation and synthesis.
4 M
2 (a)
Explain the execution of signal assignment statements in HDL.
5 M
2 (b)
Briefly discuss:
i) Constant declaration and assignment statement
ii) Signal declaration and assignment statement
i) Constant declaration and assignment statement
ii) Signal declaration and assignment statement
6 M
2 (c)
Write VHDL/Verilog code for 2×2 bit combinational array multiplier.
9 M
3 (a)
Write VHDL code for 3 bit binary counter using CASE statement.
6 M
3 (b)
Explain verilog cases. Write verilog description of priority encoder using casex statement.
6 M
3 (c)
With syntax, explain the sequential statements in HDL:
i) IF statement
ii) IF as ELSE-IF
iii) For loop
i) IF statement
ii) IF as ELSE-IF
iii) For loop
8 M
4 (a)
Write structural description of an VHDL SR latch using NOR gates.
8 M
4 (b)
Write the facts of structural description.
4 M
4 (c)
Write verilog code for N bit magnitude comparator using generate statement.
8 M
5 (a)
Write VHDL code to convert unsigned binary vector to integer conversion using procedure.
8 M
5 (b)
Explain the syntax of function in verilog with an example.
4 M
5 (c)
Write VHDL code for reading a string of character from file and store in an array Ex: COLLEGE.
8 M
6 (a)
Write VHDL code for 16×8 SRAM using mixed type description.
12 M
6 (b)
Write verilog code for ALU using mixed type description.
8 M
7 (a)
Write mixed language description of Master Slave D flip flop by invoking VHDL entity from verilog module.
10 M
7 (b)
Explain the process of invoking a verilog module from VHDL module.
10 M
8 (a)
With an example, explain mapping the function statement in HDL.
6 M
8 (b)
Discuss some important facts related to synthesis basics.
6 M
8 (c)
With an example, explain mapping if, if-else, case statement in HDL. Show the synthesized logic symbol and gate level diagram.
8 M
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