1 (a)
Compare VHDL and verilog.
6 M
1 (b)
What are values that std-logic (VHDL) and nets (verilog) can take?
6 M
1 (c)
With proper example explain the logical operators of verilog.
8 M
2 (a)
What are the facts of data flow description?
2 M
2 (b)
Starting from the basic draw the logic symbol of D'latch excitation table. K map circuit for D latch and write VHDL and verilog program for the same.
10 M
2 (c)
Write a data flow description (in both VHDL and verilog) of a full adder with enable. If the enable is low (0), the sum and carry are zero; otherwise the sum and carry are usual outputs of the adder. Use a 5 ns delay for any gate including xor. Draw the truth table of this addet and derive the Boolean function after minimization.
8 M
3 (a)
With syntax explain different types if loops in VHDL and verilog.
10 M
3 (b)
Write a program in VHDL and verilog for JK flip flop using if & else if statements.
10 M
4 (a)
What is binding? Explain the binding between entity and components in VHDL and between two modules in verilog.
10 M
4 (b)
Write VHDL behavioural description of a tristate buffer. Use this as a component for structural of 2 to 4 decoder with tristate output.
10 M
5 (a)
Write VHDL procedure and verilog task for N-bit ripple carry adder.
10 M
5 (b)
With suitable example write VHDL code for writing integers to a file.
10 M
6 (a)
Give an example of a VHDL package.
8 M
6 (b)
Write the block diagram and function table of a SRAM of 16×8 and write verilog code for the same.
12 M
7 (a)
How to invoke a verilog module from a VHDL module? Giving an example of a full adder using two half adders.
10 M
7 (b)
Discuss the facts and limitations of mixed language description.
10 M
8 (a)
Draw the flow chart and explain the steps invoked in synthesis.
10 M
8 (b)
Write a program in VHDL and obtain the gate level synthesis for BP ad ADH. BP is the input and ADH is the output. BP varies from 0 to 7 and ADH varies from 0 to 16. Assume that if BP is more than 5 the ADH is 0 for BP>2 and less than 5 the ADH is given by ADH=-5×BP+25.
10 M
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