STUPIDSID
1 (a)
Explain the behavioural and dataflow style descriptions of VHDL, with the example of an half-adder.
10 M
1 (b)
Compare VHDL and verilog.
4 M
1 (c)
Explain structure of VHDL and verilog with an example.
6 M
2 (a)
Write VHDL code for 2×2 bits combinational array multiplier (Dataflow style description).
6 M
2 (b)
List the data types used in VHDL and verilog.
4 M
2 (c)
Write a dataflow description in both VHDL and verilog, for u full adder with active high enable (en=1).
10 M
3 (a)
Distinguish between signal assignment and variable assignment statement in VHDL. Also, write VHDL; program for behavioural description of D-latch using assignment and variable assignment statements, separately.
10 M
3 (b)
Explain formats of for loop and while loop statements in both VHDL and verilog.
6 M
3 (c)
Write VHDL code to calculate the factorial of positive integers.
4 M
4 (a)
Write the structural description for full adder, using two half adders.
6 M
4 (b)
Explain binding between two modules in verilog.
4 M
4 (c)
Write VHDL structural description of 3-bits synchronous up counter using JK master slave flip flops.
10 M
5 (a)
Give an example code for a procedure and a function.
6 M
5 (b)
Write VHDL description of a full adder using procedure.
8 M
5 (c)
Write a verilog code for converting a fraction binary to real using task.
6 M
6 (a)
Why a mixed typed description is needed? Write the VHDL code to find largest element in an array.
10 M
6 (b)
Write a note on package in VHDL.
3 M
6 (c)
Write VHDL code for the addition of 5× 5 matrices using a package.
7 M
7 (a)
With a mixed language description of a full adder, explain the invoking of VHDL entity from a verilog module.
10 M
7 (b)
Write the mixed language description of a JK master-slave flip-flop with clear input.
10 M
8 (a)
What is meant by synthesis? List and explain steps involved in synthesis.
7 M
8 (b)
Write VHDL or verilog code for the signal assignment statement y=2×a+5 for an entity with one input a of 3-bits and one output y of 4-bits. Show the mapping of this signal assignment to gate level.
10 M
8 (c)
Explain extraction of synthesis information from an entity.
3 M
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