STUPIDSID
1 (a)
Give and explain the routing capacitance with fringing field effect
5 M
1 (b)
Give and explain carry save adder
5 M
1 (c)
Write specification of Row Decoder, Column Decoder and MUX/DMUX used in 64K X 8 SRAM
5 M
1 (d)
Give and explain two technique to improve the minimum frequency requirement of clock signal
5 M
2 (a)
Draw and explain full adder using dual rail complementary pass transistor logic.
10 M
2 (b)
Give various important parameters affecting switching performance of CMOS
inverter. Suggest methods to improve it.
10 M
3 (a)
Explain in detail sizing of routing conductor with respect to metal migration and ground bounce /power supply drop,
10 M
3 (b)
Draw 1T DRAM cell and explain its write, read, hold and refresh operation.
10 M
4 (a)
Draw and explain CMOS two-stage OP-AMP.
10 M
4 (b)
Explain various technique of clock generation. Discuss ?H? tree clock distribution.
10 M
5 (a)
Draw three variable-three output PLA and programme it with following functions:
fx=ac+be
Fy=abc+abc
Fz=ab+ab
fx=ac+be
Fy=abc+abc
Fz=ab+ab
10 M
5 (b)
Give and explain interconnect scaling
10 M
6 (a)
Give and explain single phase clock system and explain its drawback
10 M
6 (b)
Explain need of input protection and give the input protection circuits.
10 M
Write short note on (any three) 20
7 (a)
Switch Capacitor amplifier
7 M
7 (b)
Sense amplifier
7 M
7 (c)
Low power design consideration
7 M
7 (d)
Floating gate MOSFET
7 M
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