STUPIDSID
1(a)
Will the following circuits work as current sources? Give the correct reason for your answer.
5 M
1(b)
List down the performance parameters of VCO and explain trade off between them.
5 M
1(c)
Calculate the pole associated with the node X shown in the following figure. Assume Rs = 1KΩ, CF = 0.1pF and A = 10.
5 M
1(d)
Draw and explain the floor plan for a possible mized signal chip.
5 M
2(a)
Show the op-amp based implementation of temperature independent bandgap reference and various issues involved thereof.
10 M
2(b)
For common source stage with diode connected load, if the variation of η = (gmb/gm) with the output voltage is neglected then prove that the gain is independent of bias currents and voltages.
5 M
2(c)
Assuming λ = γ = 0, Calculate the small signal gain of the circuit shown:
5 M
3(a)
The following circuit shown in Figure uses a resistor rather than a current source to define a tail current of 1mA. Assume (W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, VTH = 0.6 V, λ = γ = 0 and VDD = 3V.
(a) What is the required input CM for which Rss sustains 0.5V?
(b) Calculate RD for a differential gain of 5:
(a) What is the required input CM for which Rss sustains 0.5V?
(b) Calculate RD for a differential gain of 5:
10 M
3(b)
Explain the concept of switched capacitor circuit. Draw and explain discrete time integrator along with the output waveform.
10 M
4(a)
With the use of small signal behaviour, prove that for differential pair the magnitude of differential gain is equal to gmRD regardless of how the inputs are applied.
10 M
4(b)
What is the need of compensating operational amplifiers? Explain the compensation of two stage operational amplifiers?
5 M
4(c)
Derive an expression for the input referred noise voltage of common source stage.
5 M
5(a)
Design two stage Operational Transconductance Amplifier (OTA) similar to that shown in the figure to meet the following specifications with a phase margin of 60° ;
Av > 5000 V/V VDD =2.5 V VSS = -2.5V
gain bandwidth (GB) = 10MHz CL = 10pF
Slew Rate (SR) > 10 V/μs Vout range = ± 2.5V
ICMR = -1 to 2 V Pdiss ≤ 2mW
Use the following table for material and device parameters. Assume COX = 2.47 fF/μm2.
Verify that the voltage gain and power dissipation given in the specifications are met by the designed circuit.
Av > 5000 V/V VDD =2.5 V VSS = -2.5V
gain bandwidth (GB) = 10MHz CL = 10pF
Slew Rate (SR) > 10 V/μs Vout range = ± 2.5V
ICMR = -1 to 2 V Pdiss ≤ 2mW
Use the following table for material and device parameters. Assume COX = 2.47 fF/μm2.
| Parameter | n-channel | p-channel | Unit |
| VTO | 0.7±0.15 | -0.7±0.15 | V |
| K' | 110 | 50 | μA/V2 |
| λ | 0.04 | 0.05 | V-1 |
Verify that the voltage gain and power dissipation given in the specifications are met by the designed circuit.
15 M
5(b)
Explain charge-pump PLL.
5 M
6(a)
Compare the performance of various op-amp topologies.
5 M
6(b)
Explain the input-output characteristics of phase detector (PD) circuit.
5 M
6(c)
Explain the concept of clock feedthrough.
5 M
6(d)
Compare between full-custom and semi-custom design.
5 M
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