STUPIDSID
1 (a)
Explain Charge sharing and charge leakage problem of dynamic Logic circuit.
5 M
1 (b)
Explain cross talk in integrated circuits.
5 M
1 (c)
Explain EEPROM using floating gate NMOSFETS.
5 M
1 (d)
Compare clock skew and jitter.
5 M
2 (a)
What is effect of interconnect parasitic on delay? How delay can be reduced? What is Elmore delay model?
10 M
2 (b)
Give and explain signal phase clock system and explain its drawback.
10 M
3 (a)
Implement 4 bit adder using Carry Look Ahead (CLA) principle.
10 M
3 (b)
State the need of input and output circuit. Explain with neat diagram the schematic and design considerations for the same.
10 M
4 (a)
Explain frequency compensation in operational amplifier.
10 M
4 (b)
Implement the following function using NOR-NOR implementation for a PLA.
F1=abc+a'b'c'
F2=a'c'=a'b
F3=ab'+ac
F1=abc+a'b'c'
F2=a'c'=a'b
F3=ab'+ac
10 M
5 (a)
What are the different clock generation schemes employed in VLSI systems. Discuss 'H' tree clock distribution in high density CMOS circuits.
10 M
5 (b)
Draw schematic for 6T SRAM cell and explain its stability criteria. Also draw and discuss its butterfly curve.
10 M
6 (a)
Draw 4×4 NOR based ROM array circuitry stored following data 1011, 1001, 0101, 0011.
10 M
6 (b)
Give and explain the maximum and minimum frequency calculation of clock signal which determine the data transfer rate through cascade system.
10 M
Write short notes on any three:
7 (a)
Low power design consideration.
7 M
7 (b)
Carry skip adder.
7 M
7 (c)
Interconnect scaling.
7 M
7 (d)
Switched capacitor circuit.
7 M
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