STUPIDSID
1 (a)
Explain Manchester carry circuits.
5 M
1 (b)
Explain how ESD (electro-static discharge) affect the MOSFET.
5 M
1 (c)
Write Verilog code for 8 bit counter.
5 M
1 (d)
Draw and explain Carry save adder.
5 M
2 (a)
Determine intrinsic gate capacitance with tox=150Å, VG=3.3V. ε=3.9×8.854×10-14F/cm, if W=4μm, L=2μm.
10 M
2 (b)
Implement following function using PLA.
X=ac+bc
Y=abc+ abc
Z=ab+ab
X=ac+bc
Y=abc+ abc
Z=ab+ab
10 M
3 (a)
Explain various technique of clock generation and clock stabilization.
10 M
3 (b)
Draw 4X4 pseudo-nMOS ROM array circuitry having stored following data 0011, 1010, 1100, 0101. Also list the no. of address pins, data and word lines.
10 M
4 (a)
What is the need of sizing routing conductors, how does it affects RC delay explain?
10 M
4 (b)
Explain EEPROM using floating gate NMOSFET.
10 M
5 (a)
Give and explain CLA Adder with generate and propagate term with their Verilog code.
10 M
5 (b)
Explain in detail the input protection circuit for CMOS, also explain output circuit with I/O circuit.
10 M
6 (a)
Give and explain single phase clock system and explain its drawback.
10 M
6 (b)
Give various important parameters affecting switching performance of CMOS circuit. Suggest method to improve it.
10 M
Write short note (any three).
7 (a)
Reliability issues in CMOS circuits.
7 M
7 (b)
Low power design consideration.
7 M
7 (c)
Switch capacitor amplifier.
7 M
7 (d)
H tree clock distribution.
7 M
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