STUPIDSID
1 (a)
Explain switched capacitor amplifier
5 M
1 (b)
Explain programming techniques of EEPROM
5 M
1 (c)
If the width and length of the interconnect is reduced by 30%, then the propagation
delay of an interconnect will increase or decrease, by how much %?
5 M
1 (d)
Explain the need of interconnect delay model.
5 M
2 (a)
What would be the conductor width of power and ground wires to a 50 MHz clock buffer that drives 100 pF of on-chip load to satisfy the metal-migration consideration (J AL = 0.5mA/μm)? What is the ground bounce with chosen conductor size? The module is 500 μm from both the power and ground pads and the supply voltage is 5 volts. The rise/fall time of clock is 1ns. (Assume sheet resistance of wire = 0.05Ω/sq).
10 M
3 (a)
Explain 4-bit CLA adder with its carry equations, logical network and writs its Verilog description.
10 M
3 (b)
Explain how ESD (electro-static discharge) affect the MOSFET. Give and explain input protection circuits
10 M
4 (a)
Give and explain the maximum and minimum frequency calculation of clock signal which determine the data transfer rate through cascade system.
10 M
4 (b)
Draw 4 × 4 pseudo-nMOS ROM array circuitry having stored following data. 1111, 1011, 101, 0111. Also list the no. Of address pins, and word lines.
10 M
5 (a)
Draw and explain CMOS two-stage OP-AMP.
10 M
5 (b)
Give and explain single phase clock system and explain its drawback
10 M
6 (a)
Explain various technique of clock generation. Discuss ?H? tree clock distribution.
10 M
6 (b)
What is cross talk in IC's? Explain various methods to reduce it.
10 M
Write short notes on (any three)
7 (a)
Schmitt trigger input protection circuit.
7 M
7 (b)
Reliability issues in CMOS circuits
7 M
7 (c)
Manchester carry Circuit
7 M
7 (d)
Interconnect Scaling.
7 M
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