STUPIDSID
1 (a)
Explain H tree clock distribution.
5 M
1 (b)
Explain how ESD (electro-static discharge) effect the MOSFET.
5 M
1 (c)
if the width and length of the interconnect is reduced by 30% then the propagation delay of an interconnect will increase or decrease, by how much %?
5 M
1 (d)
Draw and explain Carry save adder.
5 M
2 (a)
What would be the conductor width of power and ground wires to a 50 MHz clock buffer that drives 100 pF of on-chip load to satisfy the metal-migration consideration (JAL=0.5 mA/μm)? What is the ground bounce with chosen conductor size? The module is 500 μ m from both the power and ground pads and the supply voltage is 5 volts. The rise/fail time mof clock is 1ns. (Assume sheet resistance of wire =0.05 Ω sq).
10 M
2 (b)
Draw 1T DRAM cell and explain its write, read, hold and refresh operation.
10 M
3 (a)
Explain 4-bit CLA adder with its carry equations, logical network and writs its Verilog description.
10 M
3 (b)
Give and explain CMOS input protection circuits.
10 M
4 (a)
Give and explain the maximum and minimum frequency calculation of clock signal which determine the data transfer rate through cascade system.
10 M
4 (b)
Draw 4×4 pseudo-n MOS ROM array circuitry having stored following data. 0011, 1010, 1100, 0101. Also list the no. of address pins, data pins and word lines.
10 M
5 (a)
Explain the need of frequency compensation in CMOS operational amplifier.
10 M
5 (b)
Give and explain signal phase clock system and explain its drawback.
10 M
6 (a)
Explain various technique of clock generation and clock stabilization.
10 M
6 (b)
What is cross talk in IC's? Explain various methods to reduces it.
10 M
Write short notes on any three:
7 (a)
Manchester carry chain circuits.
7 M
7 (b)
Reliability issues in CMOS circuits.
7 M
7 (c)
Low power design consideration.
7 M
7 (d)
Switch capacitor amplifier.
7 M
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