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MU Electronics Engineering (Semester 3)
Electronic Devices
May 2012
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) If input Vi is 1khz square wave with 30vpp voltage applied to a given circuit with practical diode of silicon. Determine Vo and draw waveform? :-IMAGE
5 M
1 (b) For the fixed biased configuration given,determine the following?
(i) IBQ,ICQ (ii) VCEQ
(ii) VBE
(iv) VBC :-IMAGE
5 M
1 (c) Explain basic construction of a n-channel JFET and explain working of n channel JFET for VGS=0 and VGS<0 and draw ID v/s VDS characteristic of the same?
5 M
1 (d) If IE=3.2mA, hfe=150, hoe=25?mho and hob=0.5?s for transistor then determine and draw:
(i) the common emitter hybrid equivalent ckt
(ii) the common base re model ckt?
5 M
1 (e) Compare ?L? and ?C? filter ckt?
5 M

2 (a) For a standard voltage divider bias configuration of C-E amplifier with RE bypassed by a capacitor CE the following data is given
Vcc=22V, R1=56k?, R2=8.2k?, RC=6.8k?, RE=1.5k?, Ci=Co=10&mu:F,
CE=20&mu:F, ?=90
Determine
(a) re
(b) Zi
(c) Zo for ro =??
(d) Av for ro=??
(e) Re calculate parameters of part (b) through (d) if ro=1/hoe=50k? and compare the result? :- IMAGE
12 M
2 (b) A power transistor is used as a switch. Calculate the currents, output voltage and power dissipated in the transistor for the given ckt when V1=0V and 12V. Circuit and transistor parameters are: RB=240?, VCC=12V, VBE(on)=0.7V, VCE(sat)= 0.1V, ?=75. Assume the load is a motor with an efficient resistance of RC=5?? :-IMAGE
8 M

3 (a) design a full wave bridge rectifier to meet particular specifications. It should produce a peak output voltage of 12V and deliver 120mA to the load RL. Output must be with a ripple of not more than 5%. An input line voltage of 120V(rms). 60 Hz is available?
8 M
3 (b) Draw and explain working of a voltage doubler circuit?
6 M
3 (c) The zener diode regulator circuit shown has an input voltage (Vps) that varies between 10 V and 14 V and load resistance varies between 20? and 100&Omega. Assume 5.6V zener diode is used and assume IZ(min)=0.1 IZ(max). Find the value of Ri required and the minimum power rating of the diode.
6 M

4 (a) Determine the following for the given network IDSS=9mA and Vp=-3V.
(1) IDQ and VGSQ
(2) VDS
(3) VD
(4) VS
You can use graphical method.:- IMAGE
10 M
4 (b) Draw npn BJT common collector (emitter follower) amplifier circuit and derive equation for small signal voltage gain ?Av? using r? model?
10 M

5 Design a single stage CS JFET amplifier using potential divider biasing for the following specifications:-
V0=2V
Fl=20Hz
ID=3.3?0.6mA
|Av|=11
Use BFW11.
Calculate Ri, Roo(max) for the design amplifier? :-IMAGE
20 M

6 Design a single stage CE BJT amplifier using BC 147A to satisfy the following specifications:-
|Av|?120
SICO?8
VCC=24V
RL=10kW
Fl is better than 10Hz
ICQ=3mA
Estimate Ri and Ro of designed amplifier. If Ri?3k&omega is a new specification added then without changing the selected transistor suggest suitable modification in the above design. What sacrifices you have made?
20 M

write a short note (any three)
7 (a) Construction, working and transfer characteristic of n channel enhancement type MOSFET?
7 M
7 (b) Comparison of performance of CE, CB, and CC BJT amplifier?
7 M
7 (c) Construction, process of electroluminescence of light emitting diode(LED)?
7 M
7 (d) Multistage amplifier?
7 M
7 (e) Photodiodes and schottky diode?
7 M

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