STUPIDSID
Answer any one question from Q1 and Q2
1 (a)
Minimize the following function using K-map & realize using Logic gates.
F(A,B,C,D) = ∑m(1,3,7,11,15) + d(0,2,5)
F(A,B,C,D) = ∑m(1,3,7,11,15) + d(0,2,5)
4 M
1 (b)
Converting following:
(255)10=(?)16
(255)10=(?)16
2 M
1 (c)
Differentiate between standard TTL and CMOS logic circuit w.r.t.
i) Propagation delay
ii) FANOUT
iii) Figure of merit
i) Propagation delay
ii) FANOUT
iii) Figure of merit
6 M
2 (a)
Convert the following numbers into binary and hexadecimal numbers.
i) (46)8 ii) (20.5)10
i) (46)8 ii) (20.5)10
4 M
2 (b)
Define the following terms and mention its standard values for TTL family.
i) Voltage and Current parameter.
ii) Power Dissipation.
iii) Noise margin.
i) Voltage and Current parameter.
ii) Power Dissipation.
iii) Noise margin.
6 M
2 (c)
Represent the following signed number in 2's complement method:
i) +8 ii) -8
i) +8 ii) -8
2 M
Answer any one question from Q3 and Q4
3 (a)
Design a 4-bit BCD to Excess-3 code converter circuit using minimum number of logic gates.
6 M
3 (b)
Design Mod-5 synchronous counter using JK flipflops.
4 M
3 (c)
Draw the excitation table of S-R Flip-flop.
2 M
4 (a)
Design a 3-bit binary to 3-bit gray code converter using IC-74138.
4 M
4 (b)
How many Flip-flops are required to build a binary counter circuit to count from 0 to 2048. What is the frequency of the output of last Flip-flop for an input clock frequency of 6MHz?
6 M
4 (c)
Perform the following:
(1111)2 + (1111)2=?
(1111)2 + (1111)2=?
2 M
Answer any one question from Q5 and Q6
5 (a)
State and explain basic component of ASM chart? What is difference between ASM chart and conventional flow chart?
7 M
5 (b)
Write VHDL code 8:1 Multiplexer using Behavioural and Dataflow modelling style.
6 M
6 (a)
Design a sequence generator circuit to generate the sequence 1-3-5-7 using Multiplexer Controller based ASM approach.
Consideration:
i) If control input C = 0, the sequence generator circuit in the same state.
ii) If control input C = 1, the sequence generator circuit goes into next state.
Consideration:
i) If control input C = 0, the sequence generator circuit in the same state.
ii) If control input C = 1, the sequence generator circuit goes into next state.
7 M
6 (b)
Explain the following statements used in VHDL with suitable examples:
i) Process.
ii) CASE.
iii) With-Select-When.
i) Process.
ii) CASE.
iii) With-Select-When.
6 M
Answer any one question from Q7 and Q8
7 (a)
What are different types of PLDs? Design 3:8 decoder using PLD.
7 M
7 (b)
Draw and explain the basic architecture of FPGA.
6 M
8 (a)
A combinational circuits is defined by the function
F1 (A,B,C)= ∑m(0,1,2,4)
F2 (A,B,C)= ∑m(1,3,5,6)
Implement this circuit with PLA.
F1 (A,B,C)= ∑m(0,1,2,4)
F2 (A,B,C)= ∑m(1,3,5,6)
Implement this circuit with PLA.
7 M
8 (b)
A combinational circuits is defined by the function
F 1 (A,B,C)= ∑m(0,1,3,4)
Implement this circuit with PAL.
F 1 (A,B,C)= ∑m(0,1,3,4)
Implement this circuit with PAL.
6 M
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