MORE IN Digital Electronics and Logic Design
SPPU Computer Engineering (Semester 3)
Digital Electronics and Logic Design
June 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Answer any one question from Q1 and Q2
1 (a) Minimize the following function using K-map and realize using logic gates: F(A, B, C, D) = ∑m (1, 5, 7, 13, 15) + d(0, 6, 12, 14)
4 M
1 (b) Convert the following: (46)10=(?)8
2 M
1 (c) List the differences between CMOS and TTL.
6 M

2 (a) Convert the following numbers into binary numbers?
i) (37)8
ii) (25.5)10
4 M
2 (b) Explain standard TTL characteristics in detail.
6 M
2 (c) Represent the following signed number in 2's complement method:
i) +25 ii) -25
2 M

Answer any one question from Q3 and Q4
3 (a) Design a 3-bit excess 3 to 3-bit BCD code converter using logic gate.
6 M
3 (b) Design mod-5 synchronous counter using J-K flip-flop.
4 M
3 (c) Draw the excitation table of J-K Flip-flop.
2 M

4 (a) Design a 4-bit binary to Gray code converter circuit using logic gates.
4 M
4 (b) Design a Mod 20 counter using decade counter IC7490.
6 M
4 (c) Perform the following:
(11011)2 + (0101)2 = (?)2.
2 M

Answer any one question from Q5 and Q6
5 (a) State and explain basic component of ASM chart ? Also explain the salient features of ASM chart.
7 M
5 (b) Write VHDL code 4:1 multiplexer using behavioural and data flow modelling style.
6 M

6 (a) Design a sequence generator circuit to generate the sequence 1?2?3?7?1 using Multiplexer controller based ASM approach. Consideration:
(i) If control input C = 0, the sequence generator circuit in the same state.
(ii) If control input C = 1, the sequence generator circuit goes into next state.
7 M
6 (b) Explain the following statements used in VHDL with suitable Examples:
(i) CASE
(ii) With select-when
(iii) Loop statement.
6 M

Answer any one question from Q7 and Q8
7 (a) Comparison between PROM, PLA and PAL.
7 M
7 (b) Draw and explain the basic architecture of FPGA.
6 M

8 (a) A combinational circuits is defined by the function:
F1 (A, B, C) = ∑m (0, 1, 3, 7)
F2 (A, B, C) = ∑m (1, 2, 5, 6)
Implement this circuit with PLA.
7 M
8 (b) A combinational circuits is defined by the function:
F1 (A, B, C) = ∑m (0, 1, 5, 6, 7)
Implement this circuit with PAL.
6 M

More question papers from Digital Electronics and Logic Design