Solve any one question from Q1 and Q2

1 (a)
Implement each expression with NAND logic:

i) ABC+DE

ii) ABC+D'+E'

i) ABC+DE

ii) ABC+D'+E'

4 M

1 (b)
Convert the decimal number 650 to hexadecimal by repeated division by 16.

2 M

1 (c)
Draw three input standard TTL NAND gate circuit and explain its operation.

6 M

2 (a)
Using K-map convert the following standard POS expression into a minimum POS expression, a standard SOP expression and minimum SOP expression: (A'+B'+C+D) (A+B'+C+D) (A+B+C+D') (A+B+C'+D') (A'+B+C+D') (A+B+C'+D).

6 M

2 (b)
Prove the following rules of Boolean algebra:

i) A+A' B=A+B

ii) (A+B) (A+C) = A+BC.

i) A+A' B=A+B

ii) (A+B) (A+C) = A+BC.

2 M

2 (c)
Explain the advantages of open collector output.

4 M

Solve any one question from Q3 and Q4

3 (a)
Design a synchronous counter for

4->6->7->3->1->4....

Avoid lockout condition. Use JK flip flop for design.

4->6->7->3->1->4....

Avoid lockout condition. Use JK flip flop for design.

6 M

3 (b)
What are the full adder's inputs that will produce each of the following outputs?

i) ∑=0, C

ii) ∑=1, C

iii) ∑=1, C

iv) ∑=0, C

i) ∑=0, C

_{out}=0ii) ∑=1, C

_{out}=0iii) ∑=1, C

_{out}=1iv) ∑=0, C

_{out}=1.
2 M

3 (c)
Explain the logic required to convert 6-bit binary number to gray code. Use that logic to convert the following binary numbers to gray code:

i) 101010

ii) 111111

iii) 000111

iv) 111000.

i) 101010

ii) 111111

iii) 000111

iv) 111000.

4 M

4 (a)
Design a SEQUENCE DETECTOR using JK Flip-Flop to detect the following sequence, .... 1001 .... Use state table diagram, state transition table and K-map as design tools. Remove all redundant states and draw the final circuit diagram.

6 M

4 (b)
Determine the output for the following input states:

D

D

_{0}=0, D_{1}=1, D_{2}=1, D_{3}=0, s_{0}=1, s_{1}=0. Use 4:1 MUX.
2 M

4 (c)
Add the following BCD numbers:

i) 1000+0110

ii) 0111+0101

iii) 0111+0010

iv) 1000+0001.

i) 1000+0110

ii) 0111+0101

iii) 0111+0010

iv) 1000+0001.

4 M

Solve any one question from Q5 and Q6

5 (a)
What is ASM chart? Give its application and explain the MUX controller method with the suitable example.

6 M

5 (b)
What is VHDL? Write a VHDL code for 3:8 decoder using behavioural modelling style.

7 M

6 (a)
Explain different modelling style used to VHDL language with example.

6 M

6 (b)
Draw an ASM chart for the 2-bit counter with the following specifications:

i) It will court UP if X=1

ii) It will maintain the state if X=0

iii) Produces output = 1.

If the counter bits are equal unconditionally, otherwise output = 0 unconditionally. X is an external input.

i) It will court UP if X=1

ii) It will maintain the state if X=0

iii) Produces output = 1.

If the counter bits are equal unconditionally, otherwise output = 0 unconditionally. X is an external input.

7 M

Solve any one question from Q7 and Q8

7 (a)
Show how PAL is programmed for the following 3 variable logic function:

i) X=AB'C+A'BC'+A'B'+AC

ii) Y=A'B'C+AB'C+A+AB.

i) X=AB'C+A'BC'+A'B'+AC

ii) Y=A'B'C+AB'C+A+AB.

6 M

7 (b)
What is FPGA? Explain in detail the architecture of FPGA.

7 M

8 (a)
What is the difference between PAL and PLA with suitable example?

6 M

8 (b)
Design a BCD to Excess-3 code converter and implement using suitable PLA.

7 M

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