STUPIDSID
Solve any one question.Q1(a,b,c) Q2(a,b,c)
1(a)
Minimize the following logic function and realize using NAND gates:
F(A,
B,
C,
D)=∑m(1,
3,
5,
8,
9,
11,
15)+d(2,
13).
F(A,
B,
C,
D)=∑m(1,
3,
5,
8,
9,
11,
15)+d(2,
13).
4 M
1(b)
Write the rules for BCD addition and give example.
2 M
1(c)
Draw and explain 3 bit Asynchrous UP counter using MS-JK flip-flop, also draw timing diagram for the same.
6 M
2(a)
Design 16: 1 Multiplexer using 4:1 MUX. Explain the truth table of your design.
6 M
2(b)
Compare Moore and Mealy model.
2 M
2(c)
Convert the following flip-flop:
i) JK to T
ii) SR to D.
i) JK to T
ii) SR to D.
4 M
Solve any one question.Q3(a,b,c) Q4(a,b,c)
3(a)
What is an ASM chart? Draw an ASM chart and state table for 2 bit UP-down counter having mode control input M:
When M=1: UP counting and When M=0 : Down counting.
When M=1: UP counting and When M=0 : Down counting.
6 M
3(b)
Implement the following Boolcan function using PAL:
F1=∑m (0,
2,
3,
4,
5,
6,
7,
8,
10,
11,
15)
F2=∑ (1,
2,
8,
12,
13)
F1=∑m (0,
2,
3,
4,
5,
6,
7,
8,
10,
11,
15)
F2=∑ (1,
2,
8,
12,
13)
6 M
4(a)
Write VHDL code for full adder using:
i) Data Flow modeling
ii) Structural modelling.
i) Data Flow modeling
ii) Structural modelling.
4 M
4(b)
Explain entity declaration for IC7432 (OR gate).
2 M
4(c)
Implement 3 bit binary to gray code converter using PLA.
6 M
Solve any one question.Q5(a,b) Q4(a,b)
5(a)
Compare TFL and CMOS logic family and also draw CMOS- NOR gate.
7 M
5(b)
Draw three input standard TTL NAND gate circuit and explain its operation.
6 M
6(a)
State the following charteristics of digital TTL and CMOS Ics:
i) Figure of merit
ii) Noise immunity
iii) Speed operation.
i) Figure of merit
ii) Noise immunity
iii) Speed operation.
6 M
6(b)
What is logic family? Give the classification of logic family in deatail.
7 M
7(a)
Draw and explain architecure of microcontroller 8051.
7 M
7(b)
Explain any three addressing modes of 8051 with example.
6 M
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