STUPIDSID
1 (a)
Which are the four general criteria to measure design quality of a fabricated
integrated circuit (chip)? Briefly explain each of them.
7 M
1 (b)
What are the problems associated with LOCOS isolation technique? Explain
each of the fabrication steps involved in LOCOS technique with suitable
Diagrams.
7 M
2 (a)
Draw the structure of MOS capacitor and derive the expression for the
maximum depth of the depletion region for the same.
7 M
2 (b)
Define threshold voltage (VT ) of MOSFET device. Which are the four physical
components on which VT depends? Derive expression for VT .
7 M
2 (c)
How can we measure following parameters of n-channel MOSFET device? Explain with necessary test set-ups.
1. Kn
2. VT0
3. Substrate bias coefficient (γ)
4. CLM parameter (λ)
1. Kn
2. VT0
3. Substrate bias coefficient (γ)
4. CLM parameter (λ)
7 M
3 (a)
Draw CMOS Inverter circuit. Obtain expressions for VIL and Vth .
7 M
3 (b)
Describe Elmore Delay technique to estimate the delay of interconnects.
7 M
3 (c)
In CMOS inverter circuit, if the supply voltage is reduced below the summation of VT , n and |VT , p| , how the output voltage will follow the change in input voltage (i.e. draw VTC and explain its behavior)? Assume that enhancement MOSFET
devices are used in the CMOS Inverter circuit.
7 M
3 (d)
Derive expression for frequency of oscillation for three stage ring oscillator
circuit. Draw necessary circuit and waveforms.
7 M
4 (a)
Draw two-input CMOS NOR and NAND gate circuits. Identify the transistor/s
suffering from body bias effect in each of these circuits. Assume single-well
CMOS technology.
7 M
4 (b)
With appropriate circuit example, illustrate the cascading problem in dynamic
CMOS logic and the possible solution/s for the same.
7 M
4 (c)
Show that the transmission gate (TG) is a good conductor of ?1? as well as ?0?.
Implement two-input multiplexor circuit using is Tgs.
7 M
4 (d)
Realize negative edge-triggered master-slave D flip-flop using CMOS
transmission gates and CMOS inverters. Explain its working with waveforms.
7 M
5 (a)
Define controllability and observability. Draw and explain the general structure
of scan-based design technique to improve testability of sequential circuits.
7 M
5 (b)
What is the need of voltage bootstrapping? Draw MOSFET based voltage bootstrapping circuit. Explain its operation along with necessary mathematical
steps.
7 M
5 (c)
What do you understand by clock skew? Explain various clock distribution
schemes with diagrams.
7 M
5 (d)
Draw and explain general architecture of CPLD.
7 M
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