STUPIDSID
1 (a)
1. Draw Voltage Transfer Characteristics of Enhancement mode and Depletion mode MOSFETs.
2. Is PMOS is subjected to substrate-bias effect (Body effect) in CMOS Inverter? Justify your answer.
3. Briefly describe yield and manufacturability.
4. Define Positive photoresist and negative photoresist.
5. As we reduce VDD of CMOS inverter, write VDD (Min) for which CMOS inverter operates correctly?
6. Draw general layout of an H-tree clock distribution network.
7. Discuss controllability in brief.
2. Is PMOS is subjected to substrate-bias effect (Body effect) in CMOS Inverter? Justify your answer.
3. Briefly describe yield and manufacturability.
4. Define Positive photoresist and negative photoresist.
5. As we reduce VDD of CMOS inverter, write VDD (Min) for which CMOS inverter operates correctly?
6. Draw general layout of an H-tree clock distribution network.
7. Discuss controllability in brief.
7 M
1 (b)
Discuss MOSFET capacitances in brief.
7 M
2 (a)
Discuss guideline for avoiding of CMOS Latch-Up.
7 M
2 (b)
Derive the expression for τPHL for CMOS Inverter for ideal step as an input to CMOS
Inverter.
7 M
2 (c)
Discuss VLSI Design flow in detail.
7 M
3 (a)
Draw the CMOS Inverter circuit and Voltage Transfer Characteristic (VTC) for different operating regions of the nMOS and pMOS transistors. Derive critical voltage points
VOH ,VOL ,VIL , VIH .
VOH ,VOL ,VIL , VIH .
7 M
3 (b)
Consider a CMOS Inverter circuit with the following parameters:
VDD =3.3V, VTO,n=0.6V , VTO,p= - 0.7V, kn =400 microAmp/V2 , kp =160 microAmp/V2 .
Calculate the noise margin of the circuit.
VDD =3.3V, VTO,n=0.6V , VTO,p= - 0.7V, kn =400 microAmp/V2 , kp =160 microAmp/V2 .
Calculate the noise margin of the circuit.
7 M
3 (c)
Draw the Inverter circuit with Resistive Load Inverter. Derive critical voltage points VOH,
VOL, VIL and VIH for Resistive Load Inverter circuit.
7 M
3 (d)
Consider a resistive-load inverter circuit with VDD =5 V, Kn? =10 MicroA/V2 , VTO=0.8V,RL=400kΩ,and W/L=2.Calculate the critical Voltages (VOH,VOL,VIL and VIH) on the VTC and find the noise margins of the circuit.
7 M
4 (a)
Draw the energy band diagram of MOS structure at surface inversion and derive the
expression for the maximum possible depth of the depletion region.
7 M
4 (b)
Derive Req of all regions in CMOS Transmission gates and draw a graph of equivalent R
plotted as a function of output voltage.
7 M
4 (c)
Discuss CMOS SR latch circuits based on NOR2 gates.
7 M
4 (d)
Discuss Ad hoc testable design techniques.
7 M
5 (a)
Discuss basic principles of Pass transistor circuits and Logic "1" transfer.
7 M
5 (b)
Explain domino CMOS logic.
7 M
5 (c)
Describe the process of fabrication of the NMOS transistor.
7 M
5 (d)
Explain Built-in Self Test (BIST) techniques with necessary diagrams.
7 M
More question papers from Vlsi Technology And Design