STUPIDSID
1 (a)
Explain the VLSI design flow using the D'Gajski's 'Y'-chart.
7 M
1 (b)
Explain the LOCOS technique for device isolation. Why it is preferred over the Etched field oxidation technique?
7 M
2 (a)
Discuss the four components of threshold voltage (VT ) in detail.
7 M
2 (b)
Explain the Short Channel Effects on threshold voltage and mobility of the charge carriers.
7 M
2 (c)
Calculate the threshold voltage VT0 at VSB = 0, for a polysilicon gate nMOS transistor, with the following parameters:
Substrate doping density NA = 3.5 × 1016 cm-3.
Polysilicon gate doping density ND = 4 × 10 20 cm-3.
Gate oxide thickness tox = 800 A°
Oxide-interface fixed charge density Nox = 6.5 × 1010 cm-2.
Physical and material constants :
Thermal voltage kT/q = 26 mV
Energy Gap of silicon(Si) Eg = 1.12eV.
Intrinsic Carrier Concentration of (Si) ni =1.45 × 1010 cm?3
Dielectric constant of vaccum εo = 8.85 × 10-14 F/cm
Dielectric constant of silicon εsi = 11.7xεoF/cm.
Dielectric constant of silicon dioxide εox=3.97 xεo F/cm.
Substrate doping density NA = 3.5 × 1016 cm-3.
Polysilicon gate doping density ND = 4 × 10 20 cm-3.
Gate oxide thickness tox = 800 A°
Oxide-interface fixed charge density Nox = 6.5 × 1010 cm-2.
Physical and material constants :
Thermal voltage kT/q = 26 mV
Energy Gap of silicon(Si) Eg = 1.12eV.
Intrinsic Carrier Concentration of (Si) ni =1.45 × 1010 cm?3
Dielectric constant of vaccum εo = 8.85 × 10-14 F/cm
Dielectric constant of silicon εsi = 11.7xεoF/cm.
Dielectric constant of silicon dioxide εox=3.97 xεo F/cm.
7 M
3 (a)
Explain the MOSFET capacitances in detail.
7 M
3 (b)
Consider a CMOS inverter with the following parameters:
nMOS VT0,n = 0.6 V , μnCox = 60 A/V2 (W/L)n = 8
pMOS VT0,p = - 0.7 V, μp Cox = 25 μA/V2 (W/L)p = 12
Calculate the noise margins and the switching threshold (Vth ) of this circuit.
The power supply voltage VDD = 3.3 V.
nMOS VT0,n = 0.6 V , μnCox = 60 A/V2 (W/L)n = 8
pMOS VT0,p = - 0.7 V, μp Cox = 25 μA/V2 (W/L)p = 12
Calculate the noise margins and the switching threshold (Vth ) of this circuit.
The power supply voltage VDD = 3.3 V.
7 M
3 (c)
Draw the inverter circuit with depletion type nMOS load. Mention the operating regions of driver and load transistors for different input voltages. Derive critical voltage points VOH ,
VOL and VIH for depletion- load inverter.
7 M
3 (d)
Write a note on CMOS Ring Oscillator circuit.
7 M
4 (a)
Define propagation delay and derive the expression for ? PHL for CMOS Inverter. Assume ideal step as an input to CMOS Inverter.
7 M
4 (b)
Explain the basic principle of pass transistor circuit. Explain logic ?1? transfer and logic "0" transfer.
7 M
4 (c)
Explain the dynamic CMOS logic (Precharge-Evaluation) and discuss the cascading problem in dynamic CMOS logic.
7 M
4 (d)
Explain the Transmission Gate (TG). Draw six-transistor CMOS -TG implementation of the
XOR function.
7 M
5 (a)
Explain Latch up problem in CMOS inverter. Mention causes and remedy for avoiding latch up.
7 M
5 (b)
Implement the following Boolean function using CMOS.
F=(ABC+DE)
Find a equivalent CMOS inverter circuit for simultaneous switching of all inputs, assume that (W/L)p = 20 for all pMOS transistors and (W/L)n = 10 for all nMOS transistors.
F=(ABC+DE)
Find a equivalent CMOS inverter circuit for simultaneous switching of all inputs, assume that (W/L)p = 20 for all pMOS transistors and (W/L)n = 10 for all nMOS transistors.
7 M
Write short note (Any TWO)
6 (a)
On-Chip Clock Generation and Distribution.
7 M
6 (b)
Comparison of FPGA and CPLD.
7 M
6 (c)
Comparison of Full-scaling and Constant voltage scaling.
7 M
6 (d)
Built In Self Test (BIST).
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6 (e)
Domino CMOS logic.
7 M
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