STUPIDSID
1 (a)
Explain VLSI Design Flow.
7 M
1 (b)
Derive drain current using gradual channel approximation.
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2 (a)
Derive switching power dissipation equation of CMOS inverter with idea step input.
7 M
2 (b)
Derive threshold voltage equation and explain what is substrate bias effect.
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2 (c)
Calculate the threshold voltage Vto at Vsb=0, for a polysilicon gate n-channel MOS transistor, with the following parameters: substrate doping density Na=1016 cm-3, plysilicon gate doping density ND=1020 cm-3, gate oxide thickness tax=500 A° and oxide interface fixed charge density Nax=2×1010 cm-2, Thermal voltage=KT/q=0.026V, energy gap of silicon (Eg)=1.12eV, ni=1.45×1010 cm-3, εo=8.85×10-14 F/cm, εox=3.97 ε0 and εsi=11.7ε0.
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3 (a)
Draw CMOS Inverter circuit and voltage transfer characteristics. Mention
different operating region of NMOS and PMOS on VTC and derive critical
voltages VIL and VIH equation.
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3 (b)
Consider a CMOS inverter with the following parameters:
VTon=0.6 V, VTop= -0.7 V, Kn'=50 uA/V2, Kp'=16 uA/V2, (W/L)n=4, (W/L)p=5 Calculate the noise margins of the circuit. The power supply voltage is VDD=3.3V.
VTon=0.6 V, VTop= -0.7 V, Kn'=50 uA/V2, Kp'=16 uA/V2, (W/L)n=4, (W/L)p=5 Calculate the noise margins of the circuit. The power supply voltage is VDD=3.3V.
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3 (c)
Draw the Inverter circuit with Resistive Load. Derive critical voltage points. VOH, VOL, VIL and VIH for resistive Load Inverter circuit. Shows the effect of KnRL value on transfer characteristics.
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3 (d)
Design a resistive load inverter with RL=1KΩ, such that VOL=0.6V. The enhanement type driver transistor has the following parameters: Vdd=5V, VTo=1V, γ=0.2 V1/2, &lambda=0, μnCox=22 μA/V2. Determine
i) Require aspect ratio, W/L
ii) VIL and VIH and
iii) noise margin NML and NMH.
i) Require aspect ratio, W/L
ii) VIL and VIH and
iii) noise margin NML and NMH.
7 M
4 (a)
Implement the following Boolean function using CMOS F=[(C+D+E)(B+A)]' find a equivalent CMOS inverter circuit simultaneous switching of all inputs. Assume (W/L)p=15 for all pmos transistor and (W/L)n=10 for all nmos transistor.
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4 (b)
Justify importance of transmission gate. Realize following functions using TG,
i) F=AB+A'C'+AB'C and
ii) F=AB'+A'B
i) F=AB+A'C'+AB'C and
ii) F=AB'+A'B
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4 (c)
Draw i/p and o/p waveform during high to low transition of o/p for CMOS inverter and derive expression for τPHL using differential equation method.
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4 (d)
Write a short note on Built In Self Test (BIST).
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5 (a)
What is the need of voltage bootstrapping? Discuss voltage bootstrapping in detail.
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5 (b)
Draw the circuit diagram of domino CMOS logic gate gate and discuss it in detai.
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5 (c)
Draw CMOS implementation of D latch with two inverter and two CMOS TG
gates. Explain its working.
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5 (d)
Draw the gate and circuit level CMOS SR latch based on NOR2 gate and
discuss it in detail.
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