Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) The segregation co-efficient of oxygen is 0.25. Find the concentration of oxygen in the silicon ingot at a fraction solidified of 0.3. The concentration of oxygen in the silicon at the top of the crystal is 12.5x1017 atoms/cm3 at fraction solidified of 0.1.
5 M
1 (b) Draw the schematic diagram and stick diagram of NMOS depletion inverter
5 M
1 (c) Explain what is pass transistor logic ? Calculate the op voltage of the circuit if VDD = 5V and VTH = 1.5V
5 M
1 (d) Define the threshold voltage with equation and explain the body effect.
5 M
1 (e) State the difference between diffusion and ion implementation.
5 M

2 (a) With neat cross sectional diagram explain the process of CMOS fabrication using p-well process. Thus give the number of masks required.
10 M
2 (b) Consider an Aluminum silicon MOS structure with the following parameters:
ND=2.5x1014 /cm3
QOX=1010 qc/cm3
TOX=650 Ao
?ms= -0.35V
Ni=1.45 x 1010/cm3
10 M

3 (a) Draw the circuit diagram of two input NAND gate using CMOS. Draw its stick diagram & layout using ? based design rules.
10 M
3 (b) State all types of inverter with their merits and demerits. Give their applications.
10 M

4 (a) Determine pull up to pull down ratio (Zpu/Zpd) for an NMOS inverter when driven by another inverter.
10 M
4 (b) Explain latch up in CMOS in detail. What are the remedies to avoid latch-up.
10 M

5 (a) Implement the following using CMOS logic function: F= X. (Y + Z) + XW Design the circuit and draw the stick diagram using Euler?s method.
10 M
5 (b) Design 4: 1 multiplexer using MOS transmission logic. Draw the stick diagram of the same.
10 M

6 (a) Compare both the scaling methods. Show analytically how power dissipation, maximum operating frequency, current density and saturation current scale in terms of scaling factors.
10 M
6 (b) Write the Verilog code for 2 input NAND gate using the module of NAND gate design SR latch and write the Switch level Verilog code for the same.
10 M

7 (a) Short channel effect in MOSFET?s.
7 M
7 (b) Compare buried and butting contacts.
7 M
7 (c) Semicustom and full custom design
7 M

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