STUPIDSID
1 (a)
Discuss why the threshold voltage changes when a reversed biased source to substrate voltage is applied to the MOSFET.
5 M
1 (b)
Consider an NMOS structure with a p-type semiconductor substrate doped to a Na=1016 /cm3, a silicon dioxide insulator with a thickness of 500 Ao an n+ polysilicon gate doped to 2x1020 /cm3 and oxide interface charge density of 4x1010 /cm2 calculate the Flat Band Voltage.
5 M
1 (c)
Explain the λ (Lambda) based design rule for an implant mask in NMOS technology and the problems faced in case of violation of the rule during fabrication. Draw appropriate diagrams.
5 M
1 (d)
Discuss various steps of silicon planar process and its advantage in fabrication of Integrated circuits.
5 M
1 (e)
Design a 4:1 MUX using NMOS pass transistor logic and discuss the drawbacks of the circuit and remedies to improve the drawback.
5 M
2 (a)
Sketch and explain the general shape of the low frequency C-V characteristics to be expected from a metal oxide p-substrate capacitor. How does the characteristic change for the high frequency condition?
10 M
2 (b)
Consider an n-channel MOSFET with gate width w = 10 μm , gate length L = 2μm and oxide capacitance COX= 10-7F/cm2. In the linear region the drain current is found to have the following values at VDS=0.1 V.
ID=50μA at VGS=1.5V
ID=80 μA at VGS=2.5V
Calculate the inversion carrier mobility and the threshold voltage of the device.
ID=50μA at VGS=1.5V
ID=80 μA at VGS=2.5V
Calculate the inversion carrier mobility and the threshold voltage of the device.
10 M
3 (a)
What do you mean by inverter ratio? Derive the same for an CMOS inverter and discuss the symmetric CMOS inverter design.
10 M
3 (b)
A PMOS transistor is to be fabricated. Describe its fabrication giving the mask sequence. Sketch the cross sectional view of all the masking steps.
10 M
4 (a)
Draw the stick diagram and mask layout using ? (lambda) based design rules for a depletion load NMOS inverter with pull ? up to pull down ratio as 4:1 i.e. Zpu/Zpd=4/1
10 M
4 (b)
Determine the device sizes for 3-input NAND and 3 ? input NOR gates using conventional CMOS. Assume that the basic inverter is sized as (W/L)n =1, (W/L)p=2 and the goal of the design is to have a NAND 3 and NOR 3 gates with the same delay characteristics as the inverter. What problems would arise if the number of fanins (inputs) are increased to 10.
10 M
5 (a)
Compare the full scaling model with constant voltage scaling model for MOSFETS. Demonstrate clearly the effects of scaling on the device density, speed of the circuit, power consumption and current density of the gates
10 M
5 (b)
A depletion load NMOS inverter has the following parameters
μnCOX=30 μA/V2, VTO=0.8V (enhancement type)
VTO=-2.8V (depletion mode), r= 0.38 √ V
|2φf|= 0.6V and VDD=5V
(i) Determine the (W/L) ratios of both the transistors such that the static power dissipation for Vin=VOH is 250mW and VOL=0.3V
(ii) Calculate VIL and VIH and the noise margins.
μnCOX=30 μA/V2, VTO=0.8V (enhancement type)
VTO=-2.8V (depletion mode), r= 0.38 √ V
|2φf|= 0.6V and VDD=5V
(i) Determine the (W/L) ratios of both the transistors such that the static power dissipation for Vin=VOH is 250mW and VOL=0.3V
(ii) Calculate VIL and VIH and the noise margins.
10 M
6 (a)
Implement the circuit for clocked SR ? latch at switch level and write the Verilog module for the circuit designed.
10 M
6 (b)
Implement the following function using CMOS technology
F = XYZ + XW
Also draw the stick diagram for the circuit designed.
10 M
7 (a)
4 x 4 barrel shifter
10 M
7 (b)
Short channel MOSFETS.
10 M
7 (c)
CMOS latch-up and its prevention.
10 M
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