STUPIDSID
1 (a)
Draw a energy band diagram of MOS capacitor under external bias.
5 M
1 (b)
Compare buried and butting contact.
5 M
1 (c)
Implement following function using CMOS. \[ F=\overline{a.b+c.d+e} \]
5 M
1 (d)
Draw the stick diagram for CMOS NOR gate.
5 M
2 (a)
Explain the various parameter affecting the threshold voltage of MOSFET. Explain the effect of ion implementation on threshold voltage of MOSFET.
10 M
2 (b)
Explain the complete fabrication process steps for CMOS Inverter using n-well process with the help of cross sectional diagram with all masking steps.
10 M
3 (a)
A CMOS symmetric inverter has following parameter
VDD=-3.3V, Vm=0.6V, Vtp=-0.7v.
kn=200 ?A/V2 kp=80 ?A/V2
Calculate noise margin of the circuit.
VDD=-3.3V, Vm=0.6V, Vtp=-0.7v.
kn=200 ?A/V2 kp=80 ?A/V2
Calculate noise margin of the circuit.
10 M
3 (b)
Define scaling-Discuss the advantages and disadvantages of different types of scaling.
10 M
4 (a)
Draw circuit diagram, stick diagram and layout for two input NOR gate using CMOS design rules.
10 M
4 (b)
Explain the operation of CMOS inverter with clearly mentioning the five cases given below.
i) Vintn
ii) Vin=VIL
iii) Vin=VIH
iv) Vin>VDD+Vtp
v) Vin=VTH (Inverter threshold).
i) Vin
ii) Vin=VIL
iii) Vin=VIH
iv) Vin>VDD+Vtp
v) Vin=VTH (Inverter threshold).
10 M
5 (a)
Write a verilog code for 4 bit ripple counter using D-FF as a basic component.
10 M
5 (b)
Compare passive load, active load NMOS inverter circuit with advantages and disadvantages.
10 M
6 (a)
Implement following Boolean function using CMOS logic \[ y=\overline{ x.y.z+x.w.y } \] Draw stick diagram and layout of the circuit.
10 M
6 (b)
What is latch up in CMOS inverter and how to avoid it.
10 M
Write short notes on any three:
7 (a)
Hot electron effect.
7 M
7 (b)
Y-chart for design flow.
7 M
7 (c)
Design rules and their necessity.
7 M
7 (d)
Oxidation.
7 M
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