MU Electronics Engineering (Semester 7)
VLSI Design
December 2013
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1 (a) Consider a MOS capacitor made on p - type substrate with a doping of 1016/cm3. The SIO2 thickness is 500 Ao and the metal gate is made up of aluminium. Calculate the minimum capacitance at threshold.
5 M
1 (b) An NMOS with VT of 1.5 V is operated as VGS=5V and IDS=100 ?A. Determine if the MOSFET is in the linear region or saturation region. Assume that K= 20?A/V2.
5 M
1 (c) Consider a resistive load NMOS inverter with an output voltage of 0.2 V when the input is VOH=VDD=5V. Find the DC power dissipation of the circuit.
5 M
1 (d) "Two critical voltage points on the voltage transfer characteristics of a realistic inverter are identified at points where the slope of VOUT and VIN characteristic becomes equal to -1?. Justify the selection of these critical voltage points based on the noise considerations.
5 M
1 (e) Explain the layout design rule for minimum gate extension of polysilicon over active and the problems faced in case of violation of rule during fabrication. Draw appropriate diagrams.
5 M

2 (a) Explain the various parameters affecting the threshold voltage of a MOS structure. Also explain the influence of substrate bias and ion implantation (in the channel region) on the threshold voltage of the device.
10 M
2 (b) Consider an n-channel MOSFET at 300 K with the following parameters:
Channel length = 1.5 ?m, Channel doping = 1016/ cm3
Channel width = 25 ?m , Oxide thickness = 500 Ao
channel mobility ?n=600 cm2/Vs, Oxide charge =10-11 cm 2
Metal SC work function difference ?ms= -1.13V.
Calculate the saturation current of the device at the gate bias of 5V.
10 M

3 (a) Derive an expression for the switching voltage of a CMOS inverter. Design a CMOS inverter with a switching voltage of VDD/2.
10 M
3 (b) Draw the schematic and stick diagram of a 2 ? input CMOS NOR gate and determine the sizes of the transistors such that it has approximately same tPLH and tPHLas an inverter with the following sizes.
(W/L)nmos = 0.5?m/0.25?m and (W/L)pmos = 1.5?m/0.25?m
10 M

4 (a) Design a two input NAND gate in NMOS technology based on a reference NMOS depletion load inverter with inverter ratio KR=4. Draw the stick diagram and mask layout of the circuit designed following the ? based design rules.
10 M
4 (b) Compare the passive and active loads in an NMOS inverter circuit stating their advantages and disadvantages.
10 M

5 (a) Explain the basic sequence for building a self aligned p-channel MOSFET with the help of appropriate diagrams.
10 M
5 (b) Implement circuit for 2:1 multiplexer using transmission gate logic and write Verilog module for the circuit designed.
10 M

6 (a) Compare and explain the effect of full scaling and constant voltage scaling MOSFET dimensions, potentials, doping densities and other key device characteristics.
10 M
6 (b) Implement of following boolean function in CMOS logic $Y=\bar{\left(A+D+E\right),(C+B)}$
Drow the stick diagram of the circuit and find an equivalent CMOS inverter circuit for simultaneously switching of all inputs, assumng that (W/L)p=15 for all PMOS transisters and (W/L)n=10 for all nmos transisters.
10 M

7 (a) CMOS latch-up and its prevention
10 M
7 (b) MOS CV characteristics
10 M
7 (c) Short channel Effects
10 M

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