SPPU Computer Engineering (Semester 4)
Microprocessor and Interfacing Techniques
June 2015
Total marks: --
Total time: --
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Answer any one question from Q1 and Q2
1 (a) What are different components of MS-DOS ? Explain DOS loading with the help of neat diagram.
8 M
1 (b) Compare 8086, 80386 and i7 processor on the basis of architectural features.
4 M

2 (a) Draw and explain block diagram of 8259APIC.
8 M
2 (b) Write the initialization instructions of 8259A PIC, to meet the following specifications:
i) Interrupt type 32
ii) Edge Triggered, single and ICW4 needed, interval of 8
iii) Mask IR1 & IR3 interrupts.
4 M

Answer any one question from Q3 and Q4
3 (a) Draw and explain I/O of BSR mode of 8255 with appropriate control word formats.
4 M
3 (b) Draw and discuss internal block diagram of 8251 USART.
6 M
3 (c) Define Resolution and Offset error terms of ADC.
2 M

4 (a) Design a control word format for square wave generator with 1ms period, the input frequency for 8253 is 1 MHz.
4 M
4 (b) Draw and explain the following 8279 commands:
(i) Keyboard/Display mode set command
(ii) Read FIFO/Sensor RAM command.
4 M
4 (c) Explain with neat diagram sequence of DMA operation.
4 M

Answer any one question from Q5 and Q6
5 (a) Draw and discuss the interface between 8086 and 8087.
7 M
5 (b) With proper timing diagram explain Read cycle in minimum mode of 8086 microprocessor.
6 M

6 (a) With the help of neat diagram explain minimum mode configuration of 8086.
6 M
6 (b) Draw and explain format of control and status word of 8087 NDP
4 M
6 (c) Explain the following 8087 instructions with one example Each:
ii) FLDZ
iii) FADD
3 M

Answer any one question from Q7 and Q8
7 (a) Explain the features of 82801 IJR I/O Controller Hub.
5 M
7 (b) Draw and explain block diagram of X58 Chipset.
8 M

8 (a) Draw and explain block diagram of i5 motherboard.
8 M
8 (b) Write a short note on Intel's QPI Technology.
3 M
8 (c) Explain ICH10 PCI Interface.
2 M

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