STUPIDSID
1 (a)
What is embedded system? Why is it so hard to define ?
4 M
1 (b)
Define time-to-market and NRE cost matrics? The life time of a product is 58weeks. If the product is delayed by 5weeks, determine the percentage revenue loss? Determine the per product cost if NRE cost is Rs 500000.00 and unit cost is Rs 8000.00 and company produces 6000 units of that product.
8 M
1 (c)
Example how the top-down design process improves the productivity.
8 M
2 (a)
Explain the purpose of controller and datapath in a signal purpose processor
4 M
2 (b)
Write a simple algorithm to find GCD of two integer numbers. Write FSMD for this algorithm and explain how it can be optimized. Also write its optimized FSMD.
8 M
2 (c)
Explain in brief, standard software development process used in embedded system
8 M
3 (a)
What is watch -dog timer? What is its use? A 16-bits timer operates at a clock frequency of 20 MHz. Determine the resolution and range of this timer. If a ÷ 4 prescalar is also used, what is the range and resolution of this design?
6 M
3 (b)
Highlight the advantages of using data in digital form over its analog form. Explain the working of successsive approximation type of analog to digital converter with an example
10 M
3 (c)
Explain the features of flash memory and DRAM.
4 M
4 (a)
Explain in brief, the memory hierarchy and cache operation. Given the following three cache designs, find the one with the best performance, by calculating the average cost of access.
(i) 4 kbytes, 8-way set associative cache with 6% miss rate. Cache hit costs 1-cycles, cache miss costs 12-cycles.
(ii) 8 kbytes, 4 way set associative cache with 4% miss rate. Cache hit costs 2-cycles,cache miss costs 12-cycles.
(iii) 16 kbyets, 2-way set associative cache with 2% miss rate. Cache hit costs 3-cycles, cache miss costs 12 cycles.
(i) 4 kbytes, 8-way set associative cache with 6% miss rate. Cache hit costs 1-cycles, cache miss costs 12-cycles.
(ii) 8 kbytes, 4 way set associative cache with 4% miss rate. Cache hit costs 2-cycles,cache miss costs 12-cycles.
(iii) 16 kbyets, 2-way set associative cache with 2% miss rate. Cache hit costs 3-cycles, cache miss costs 12 cycles.
10 M
4 (b)
Design a 2k×16 ROM using an address decoder
4 M
4 (c)
Write the features of USB and IEEE 802.11 protocol
6 M
5 (a)
With an example, explain shared data problem. Also explain how an iterrupt facility can solve this shared data problem
10 M
5 (b)
Define interrupt latency. Mention the factors that affects interrupt latency.
4 M
5 (c)
Explain in brief, function-queue-scheduling architecture.
6 M
6 (a)
Briefly compare the methods for intertask communication.
10 M
6 (b)
Explain in brief, three different states of tasks in RTOS.
5 M
6 (c)
Briefly compare the three methods of protecting shared data.
5 M
7 (a)
What are the two rules, that interrupt routines in most RTOS environment must follow, that do not apply to task codes?
5 M
7 (b)
Illustrate with the suitable examples and explain what happens when each rule of question no.7a is violated.
15 M
8 (a)
With suitable example, explain encapsulating semaphores.
8 M
8 (b)
Briefly explain any six problems with semaphores.
7 M
8 (c)
Give the hard real -time scheduling considerations.
5 M
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