1(a)
Explain a microprocessor based embedded system with diagram.
8 M
1(b)
With necessary block diagram, explain the embedded system life cycle.
8 M
1(c)
Explain the important steps in developing a embedded system.
4 M
2(a)
Analyze how errors propogate under: i) Addition process ii) Multiplication process.
8 M
2(b)
With the help of diagram, explain
i) Index mode data transfer operation.
ii) Program counter relative operation.
i) Index mode data transfer operation.
ii) Program counter relative operation.
8 M
2(c)
With timing diagram, explain i) Writing to a register ii) Reading from a register.
4 M
3(a)
With diagram, explain direct mapping implementation and associative mapping cache implementation.
8 M
3(b)
With diagram, explain the operation of DRAM. With timing diagram, explain read operation.
8 M
3(c)
Explain the concept of dynamic memory allocation.
4 M
4(a)
Deveop hardware and software specification for designing a counter and give data control flow diagram.
8 M
4(b)
With diagram explain i) Water fall life cycle model ii) Spiral life cycle model.
8 M
4(c)
Comapare functional model and architectural model.
4 M
5(a)
Explain how memory is managed at.
i) System level ii) Process level.
i) System level ii) Process level.
8 M
5(b)
Explain operating system architecture with diagram.
8 M
5(c)
Explain multithreaded OS.
4 M
6(a)
Organize general purpose register as, i) Four different contexts ii) Overlapping contexts.
8 M
6(b)
Explain the structure of TCB with diagram.
8 M
6(c)
With diagram, explain real time stack and application stack.
4 M
7(a)
Analyze the basic flow of control construct in i) Constant time statement ii) Sequence of statement iii) For loops iv) While loops.
8 M
7(b)
Explai the 3 methods used to compute time loading .
8 M
7(c)
What is a co-routine? Explain.
4 M
8(a)
Explain a typical memory map with diagram and explain the design of memory map with reference to memoryloading.
8 M
8(b)
Explain caches and their performance.
8 M
8(c)
Write explanatory note on hardware accelerators.
4 M
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