STUPIDSID
1 (a)
What is an embedded system?Define the three main characteristics embedded system that distinguish such system from other computing systems
4 M
1 (b)
Derive the percentage revenue loss equation for a rise angle of 35°.computer the percentage revenue loss if the products life time is 10 weeks and the delay in markets in 5 weeks
8 M
1 (c)
Define the three main IC technologies,What are the benefits of using each of the three different IC technologies?
8 M
2 (a)
Write a simple algorithms for finding the greatest common divisor of two number.write the FSMD for this algorithms and expalin how it can be optimize and write the optimized FSMD
10 M
2 (b)
Design a soda machine controller,given that soda costs 75 cent and your machine accepts quarters only.Draw a black box view,come up with a state diagram and state table,minimize the logic then draw the final circuit
10 M
3 (a)
Explain how a stepper motor is controlled using driver.Give relevent hardware and software details
8 M
3 (b)
The analog input range for an 8bit ADC is from -2.5 to +7.5 V.Detemine the resolution of ADC and digital output in hexadecimal when the input voltage is 1.2V.trace successive approximation steps and show the binary output of the ADC
8 M
3 (c)
A watchlog timer that uses two casecaded 16bit up counters is connnected to an 11.981MHz oscillator. A timeout should occur If the function watchlog reset is not called within 5minutes.what value should be loaded into the upcounter pair when the function is called?
4 M
4 (a)
Describe fully associated cache mapping techniques
6 M
4 (b)
Given the following three cache design,find the one with the best perfomance by calculating the average cost of access.show all calculation :
4K byte ,8-ways set associative cache with a 6% miss rate ; cache hit costs one cycle,cache miss costs 12 cycles.
8K byte,4-ways set associative cache with a 4% miss rate;cache hit costs two cycles,cache miss costs 12 cycles.
16 K byte,2-ways set associative cache with a 2% miss rate; cache hit costs three cycles cache miss costs 12 cycles
4K byte ,8-ways set associative cache with a 6% miss rate ; cache hit costs one cycle,cache miss costs 12 cycles.
8K byte,4-ways set associative cache with a 4% miss rate;cache hit costs two cycles,cache miss costs 12 cycles.
16 K byte,2-ways set associative cache with a 2% miss rate; cache hit costs three cycles cache miss costs 12 cycles
8 M
4 (c)
With a neat digarm,explain the advantage RAM architecture.also explain how this is extended to improve the perfomance through synchronous DRAM
6 M
5 (a)
Describe shared data problem with an example.show how disable/enable interrupt can be used for solving this problem
10 M
5 (b)
What is interrupt latency?What factors affecting it?
4 M
5 (c)
Consider three processes with high medium and low priorites respectively require an execution time of 150?sec.250?sec and 350?sec.if the interrupts are disabled for 200 ?sec and the deadline for the low priority process is 850?sec,determine its worst case interrupt latency.can it meet the dadline,if the two interrupts occur?Illustrate with a timing diagram
6 M
6 (a)
What are semaphores ?Explain the semaphores problem in RTOS
7 M
6 (b)
Explain the RTOS function "take semaphores "with an example.
6 M
6 (c)
What is a task?Explain the three different task states
7 M
7 (a)
Describe the two rules that an RTOS enviroment must flow for interrupt routincs.
8 M
7 (b)
Explain the advantages and disadvantages of using larger number of tasks in RTOS
6 M
7 (c)
Identify the bug in the following progarm and expalin:Void task (void)
{
:
:
VcountErrors(a);
:
:}
Void Task 2(void)
{
:
:
vcountErrors(11);
:
:}
static int cErrors;
void vcounterrors(int Cnew Errors )
{CErrors +=CNewErrors;
}
{
:
:
VcountErrors(a);
:
:}
Void Task 2(void)
{
:
:
vcountErrors(11);
:
:}
static int cErrors;
void vcounterrors(int Cnew Errors )
{CErrors +=CNewErrors;
}
6 M
8 (a)
Explain "encapsulating semaphores" with an algorithms
8 M
8 (b)
Expalin the method to save code space and method to save power
8 M
8 (c)
what is an evet?Explain the three standard features of it
4 M
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