1 (a)
Convert (1234.56)

_{10}octal, hexadecimal.
4 M

1 (b)
Represent (29)

_{10}into XS-3 and Gray code.
4 M

1 (c)
Design full adder using half adders.

4 M

1 (d)
Design a full substractor using a decoder and additional gates.

4 M

1 (e)
Simplify and implement using gates

\[Y= \overline{AB} \left(B + C \right) AB (\overline{B + C})\]

\[Y= \overline{AB} \left(B + C \right) AB (\overline{B + C})\]

4 M

2 (a)
What is canonical SOP and POS form? Explain with example.

5 M

2 (b)
Implement the following using only one 8: 1 MUX and few gate

F(A, B, C, D)= ?m(0, 3, 5, 7, 9, 13, 15)

F(A, B, C, D)= ?m(0, 3, 5, 7, 9, 13, 15)

5 M

2 (c)
Using the k-map method minimization techniques simplify and draw the circuit for the following function,

F(A, B, C, D, E)= ?m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14, 16, 17, 18, 19)+d(24, 25)

F(A, B, C, D, E)= ?m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14, 16, 17, 18, 19)+d(24, 25)

10 M

3 (a)
Simplify using Quine Mc-Cluskey method. Realize the equation using any universal gate.

F(A, B, C, D) =?M(0, 2, 3, 6, 7, 8, 9, 12, 13)

F(A, B, C, D) =?M(0, 2, 3, 6, 7, 8, 9, 12, 13)

10 M

3 (b)
Design a BCD adder using 4 bit binary adders and explain.

10 M

4 (a)
Design a 3 bit even and odd parity generator.

10 M

4 (b)
State truth table of 3 bit gray to binary conversion and design using 3:8 decoder and additional gates.

10 M

5 (a)
Design MOD-6 synchronous counter and explain its operation.

10 M

5 (b)
Draw a 4 bit universal shift register and explain

10 M

6 (a)
Draw a 4 bit ring counter using J K ff, draw the timing diagram for the same.

10 M

6 (b)
Compare TTL and CMOS logic families.

10 M

Write short notes on the following (any four) :-

7 (a)
ALU (Arithmatic Logic Unit)

5 M

7 (b)
PAL and PLA

5 M

7 (c)
Race detecting and correcting code

5 M

7 (d)
Error detecting and correcting code

5 M

7 (e)
Applications of flip flops and registers.

5 M

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