MORE IN Digital Logic Design & Analysis
MU Computer Engineering (Semester 3)
Digital Logic Design & Analysis
May 2012
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Convert (54.45)10 into binary, base 4, octal and hexadecimal number systems.
4 M
1(b) Subtract using 1's and 2's complement:
(15)10 - (21)10
4 M
1(c) Perform BCD addition of the decimal numbers 45 and 27.
4 M
1(d) Represent (25)10 in Excess-3 and Gray Code.
4 M
1(e) Perform the following operations
(i) (11001)2 - (101)2
(ii) (11001)2 x (101)2
4 M

2(a) Design a 4 bit binary to gray code converter.
10 M
2(b) Design a full subtractor and implement using gates.
10 M

3(a) Simplify the following expression using Quine McCluskey method and implement with universal gates only.F(A,B,C,D)=?m(1,3,4,5,6,7,9,11,12,13,14,15).
10 M
3(b) Implement the following using 8 : 1 MUX
F (A, B, C, D) = ? m(0, 1,2, 4,6, 7, 8, 10, 14, 15)
10 M

4(a) Design a 2 bit magnitude comparator and implement using NAND gates only.
10 M
4(b) Design 32:1 multiplexer using 4:1 multiplexers.
10 M

5(a) Design a mod-6 synchronous counter using JK FF.
10 M
5(b) Convert: (i) SR to JK flip flop(ii)SR to D flip flop.
10 M

6(a) Draw a 4 bit ring counter. Draw the timing diagram and explain the working of counter.
10 M
6(b) Explain the working of universal shift register with the help of suitable diagram.
5 M

7(a) Error detecting and correcting codes:
5 M
7(b) TTL and CMOS
5 M
7(c) ALU
5 M
7(d) DeMorgan's Theorem
5 M

More question papers from Digital Logic Design & Analysis