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MU Computer Engineering (Semester 3)
Digital Logic Design & Analysis
December 2011
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

1(a) Convert (650.17)8 into decimal, binary and hexadecimal.
6 M
1(b) Explain ALU with the help of a block diagram.
6 M
1(c) State and explain distributive and associative laws for Boolean expression.
4 M
1(d) Determine the truth table for the circuit given in Fig. 1:

4 M

2(a) Design 16:1 MUX using 4:1 MUX.
10 M
2(b) Simplify using K-map, obtain minimal SOP equation and realise only by using NAND gates.f(A, B, C, D) = ?M (1,2,3,8,9,10,11,14) + d(7,15)
10 M

3(a) Using Quine McCluskey method, determine the minimal SOP form for:F(A,B,C,D,E,F,G) = ? m(20,28,38,39,52,60,102,103,107)
10 M
10 M

4(a) What is a shift register? Explain 4-bit bidirectional shift register.
10 M
4(b) Design a MOD-6 synchronous up counter and explain its operation.
10 M

5(a) Implement the following expression using 8:1 MUX:F(A,B,C,D) = π m(0,1,3,6,9,11,12,13,15)
10 M
5(b) Explain with a neat diagram 2 input TTL NAND gate in detail.
10 M

6(a) Convert T flip-flop to D flip-flop.
10 M
6(b) Compare the different logic families with respect to the following parameters - Fan in, Fan out, Noise margin, speed and power dissipation.
10 M