STUPIDSID
Answer any one question from Q1 and Q2
1 (a)
State conditions to be satisfied for interfacing, by driving & load gate. Draw and explain the interfacing of CMOS driving TTL.
6 M
1 (b)
Minimize the following functions using k-map and implement using basic logic gates f(A,B,C,D)= ∑m(0,1,2,4,8,9,12,13)+d(3,6,7).
6 M
2 (a)
Convert the following Number into its equivalent Hexadecimal, Decimal & Binary Number (show step-by-step process of conversion):
i) (357.2)8 ii) (458.54)8
i) (357.2)8 ii) (458.54)8
6 M
2 (b)
Draw and explain the look ahead carry generator.
6 M
Answer any one question from Q3 and Q4
3 (a)
Explain the difference between asynchronous and synchronous counter & Convert J-K flip flop into D-FF. Show the design.
6 M
3 (b)
Draw an ASM chart of 2-bit up-down counter having mode control input.
6 M
4 (a)
Draw and explain the behavior of M-S JK flip flop with waveform.
6 M
4 (b)
Draw and explain Johnson counter with initial state ?1110?, from initial state explain all possible states.
6 M
Answer any one question from Q5 and Q6
5 (a)
Explain the difference between CPLD and FPGA.
6 M
5 (b)
What is meant by CPLD? Draw & Explain the block diagram of CPLD.
7 M
6 (a)
Give the comparison between PROM, PLA and PAL.
6 M
6 (b)
Design the full adder using PLA.
7 M
Answer any one question from Q7 and Q8
7 (a)
Explain with example Dataflow and behavioural modelling styles used in VHDL programming.
6 M
7 (b)
Explain with example 'signal' and 'variable' in VHDL.
7 M
8 (a)
Define entity declaration for AND gate. Also write architecture of AND gate in structural & Data modelling styles.
6 M
8 (b)
What is the difference between behavioural model and structural model in VHDL?
7 M
More question papers from Digital Electronics & Logic Design