STUPIDSID
Solve any one question from Q1 and Q2
1 (a)
Perform the following operations using 2's complement method.
i) -(48)10-(23)10
ii) -(48)10(-23)10
i) -(48)10-(23)10
ii) -(48)10(-23)10
6 M
1 (b)
Compare totem pole and open collector output configurations in TTL.
6 M
2 (a)
Draw and explain 2 inputs TTL NAND gate with Totem Pole Output.
6 M
2 (b)
Design Full adder using suitable Decoder.
6 M
Solve any one question from Q3 and Q4
3 (a)
What is Race around condition? How it can be avoided? Convert D Flip-Flop to T Flip-Flop.
6 M
3 (b)
Explain with a neat diagram working of 3 bit bidirectional shift register.
6 M
4 (a)
Explain the difference between Combinational and Sequential Circuit. Design S-R Flip-Flop using J-K Flip-Flop.
6 M
4 (b)
Design a sequence detector to detect the sequence ------- 110 ------- using J-K Flip-Flop.
6 M
Solve any one question from Q5 and Q6
5 (a)
Explain difference between PAL & PLA.
6 M
5 (b)
Design a 4 bit BCD to Excess-3 code converter using PLA.
7 M
6 (a)
Explain difference between FPGA & CPLD.
6 M
6 (b)
Design the following function using PLA.
F1=∑m(1, 2, 4, 6) F2=∑m(0, 1, 6, 7) F3=∑m(2, 6)
F1=∑m(1, 2, 4, 6) F2=∑m(0, 1, 6, 7) F3=∑m(2, 6)
7 M
Solve any one question from Q7 and Q8
7 (a)
Explain entity and architecture in VHDL with syntax and example.
6 M
7 (b)
Explain Process statement in behaviour model of VHDL with respect to syntax, sensitivity list, declarative part and statement part.
7 M
8 (a)
Explain the difference between VHDL Modelling styles-Data Flow, Behavioural and Structural
6 M
8 (b)
Explain data objects in VHDL - signals, variables and Constants.
7 M
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