STUPIDSID
Solve any one question from Q.1(a,b) & Q.2(a,b)
1(a)
Do the following conversions:
i) (27.125)10=(?)2
ii) (3A.2F)16/sub>=(?)10 iii) (1101.0011)2=(?)10
i) (27.125)10=(?)2
ii) (3A.2F)16/sub>=(?)10 iii) (1101.0011)2=(?)10
6 M
1(b)
How will you connect the output of CMOS logic circuit as an input to TTL logic circuit? Explain your reason with suitable diagram.
6 M
2(a)
Minimize the following function using Quine McClusky and implement using basic logic gates.
f(A, B, C, D) = πM (1, 2, 3, 8, 9, 10, 11, 14). d (7, 15).
f(A, B, C, D) = πM (1, 2, 3, 8, 9, 10, 11, 14). d (7, 15).
6 M
2(b)
design full adder using Decoder IC 74138.
6 M
Solve any one question from Q.3(a,b) & Q.4(a,b)
3(a)
Explain the difference between asynchronous and synchronous counter and convert SR flip-flop into T flip-flop. Show the design.
6 M
3(b)
Design and draw logic diagram of Mod 72 counter uisng IC 7490.
6 M
4(a)
Draw and explain Johnson counter with initial state 1110 from initial state. Explain all possible states.
6 M
4(b)
Design sequence generator to generate sequence.............1101011........ using shift register IC 74194.
6 M
Solve any one question from Q.5(a,b)& Q.6(a,b)
5(a)
What is ASM chart?Explain MUX controller method using suitable example.
6 M
5(b)
Implement BCD to Excess-3 code convertor using suitable PLA.
7 M
6(a)
Implement the following function using PLA: f1=∑m(0, 3, 4,7)
f2 = ∑ (1, 2, 5, 7).
f2 = ∑ (1, 2, 5, 7).
6 M
6(b)
Draw the basic structure of CPLD. Explain its feature in brief.
7 M
Solve any one question from Q.7(a,b) Q.8(a,b)
7(a)
What is VHDL? Explain entity architecture for 2-bit AND and NOR gate.
6 M
7(b)
Explain the difference between VHDL modeling styles-data flow, behavioral and structural.
7 M
8(a)
Write a VHDL code for 4-bit full adder using structual modeling style.
6 M
8(b)
Explain the following statements used in VHDL with suitable example:
i) Signal assignment
ii) Process.
i) Signal assignment
ii) Process.
7 M
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