 MORE IN Digital Electronics & Logic Design
SPPU Information Technology (Semester 3)
Digital Electronics & Logic Design
June 2015
Total marks: --
Total time: --
INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Answer any one question from Q1 and Q2
1 (a) Represent the following decimal numbers in single precision floating point format:
i) 255.5
ii) 110.65
6 M
1 (b) What do you mean by open collector output ? Explain with suitable circuit diagram. What is the advantage of this output?
6 M

2 (a) Perform 2's complement arithmetic of:
i) (7)10-(11)10
ii) (-7)10-(11)10
iii) (-7)10+(11)10
6 M
2 (b) Draw suitable circuit diagram and explain the drawback of WIRED_OR TTL GATE?
6 M

Answer any one question from Q3 and Q4
3 (a) What is race around condition? Explain with the help of timing diagram. How is it removed in basic flip-flop circuit?
6 M
3 (b) Design a sequence generator using shift register and decoder circuit to generate the sequence ......1101011...... .
7 M

4 (a) How will you convert the basic SR-flip-flop (SR-FF) into JK- Flip-flop?
6 M
4 (b) Design a MOD-11 counter using IC7490. Show states with the help of timing diagram.
7 M

Answer any one question from Q5 and Q6
5 (a) Draw the basic structure FPGA. Explain its feature in brief.
6 M
5 (b) Implement the following function using programmable logic Device:
i) F1 = ∑(0, 3, 4, 7)
F2= ∑m(1, 2, 5, 7)
6 M

6 (a) Draw the basic structure of CPLD. Explain its features in Brief.
6 M
6 (b) Design a BCD to Excess-3 code converter using suitable programmable logic device.
6 M

Answer any one question from Q7 and Q8
7 (a) State and explain different data types supported by VHDL.
6 M
7 (b) Write features of VHDL. Explain entity architecture declaration for 2 bit NOR and AND gate.
7 M

8 (a) State and discuss different types of operators used in VHDL. Give precedence of these operators.
6 M
8 (b) Describe different modelling styles of VHDL with suitable example.
7 M

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