STUPIDSID
Solve any one question from Q1 and Q2
1 (a)
Draw and explain the working of 2 input CMOS NAND gate.
6 M
1 (b)
Design the following logic expression using single 8:1 multiplexer. F(A,B,C,D) = ∑m(0,2,3,6,8,9,14) + d(12,13)
6 M
2 (a)
With the neat diagram explain the interfacing of the CMOS as a driver and TTL as a load.
6 M
2 (b)
Design a 2 bit magnitude comparator using suitable decoder.
6 M
Solve any one question from Q3 and Q4
3 (a)
Draw and explain the diagram of JK Flip-flop using nand gates and explain how race around condition is avoided ?
6 M
3 (b)
Design a sequence detector to detect the sequence 101 using Mealy machine.
6 M
4 (a)
Design a pulse train generator to generate the following sequence ......10110.... using shift register.
6 M
Explain:
4 (b) (i)
Rules for state assignments.
3 M
4 (b) (ii)
State reduction.
3 M
Solve any one question from Q5 and Q6
5 (a)
Design BCD to Excess-3 code converter using PAL.
8 M
5 (b)
Explain the difference between PLA and PAL.
5 M
6 (a)
Design the following multiple output function using PLA.
F1( a,b,c,d)= ∑m(3,7,8,9,11,15)
F2(a,b,c,d))= ∑m(3,4,5,7,10,14,15)
F1( a,b,c,d)= ∑m(3,7,8,9,11,15)
F2(a,b,c,d))= ∑m(3,4,5,7,10,14,15)
7 M
6 (b)
Explain the general architecture of CPLD.
6 M
Solve any one question from Q7 and Q8
7 (a)
Explain the different modelling styles in VHDL with suitable examples.
6 M
7 (b)
Write the VHDL code for a negative edge-triggered 'D' flip-flop with Synchronous active low reset input.
7 M
8 (a)
Explain the syntax of the process statement. What are the statements which can be used under the process?
6 M
8 (b)
Write a VHDL code for full subtractor using structural modelling style.
7 M
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